Semiconductor device mitigating parasitic capacitance and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-12014953-B2
Application number	US-202117555844-A
Country	US
Kind code	B2
Filing date	Dec 20, 2021
Priority date	Aug 20, 2021
Publication date	Jun 18, 2024
Grant date	Jun 18, 2024

Abstract

A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes: providing a first wafer including a substrate; forming a hole in the first wafer, which extends through the substrate; forming an insulating dielectric layer over a side wall of the hole; filling the hole with a conductive layer; removing at least part of the insulating dielectric layer situated in correspondence with the substrate, forming an air gap between the conductive layer and the substrate; and forming a closure layer, which closes the air gap. With the present invention, parasitic capacitance present between the conductive layer, the insulating dielectric layer and the substrate is significantly reduced, resulting in an improvement in performance of the semiconductor device.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
providing a first wafer including a substrate;
forming a hole in the first wafer, which extends through the substrate;
forming an insulating dielectric layer over a side wall of the hole;
filling the hole with a conductive layer to dispose the insulating dielectric layer formed outside of the conductive layer and sandwiched between the substrate and the conductive layer;
removing at least part of the insulating dielectric layer situated in correspondence with the substrate, forming an air gap between the conductive layer and the substrate; and
forming a closure layer, which closes the air gap,
wherein the air gap is formed outside of the conductive layer, and disposed in the insulating electric layer that is sandwiched between the substrate and the conductive layer, resulting in a significant reduction in parasitic capacitance between the conductive layer, the insulating dielectric layer and the substrate.

2. The method of claim 1 , wherein the insulating dielectric layer is a single-layer structure or a stack of at least two layers.

3. The method of claim 2 , wherein in case of the insulating dielectric layer being a stack of at least two layers, a portion of any one of the at least two layers situated in correspondence with the substrate is removed.

4. The method of claim 3 , wherein the insulating dielectric layer comprises, stacked sequentially over the side wall of the hole, a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer, and wherein a portion of the silicon nitride layer in the insulating dielectric layer in correspondence with the substrate is removed.

5. The method of claim 1 , wherein in the air gap, the substrate is exposed, or the conductive layer is exposed, or both the substrate and the conductive layer are exposed.

6. The method of claim 1 , wherein in the air gap, neither the substrate nor the conductive layer is exposed.

7. The method of claim 1 , wherein there is no conductive layer between the air gap and the substrate.

8. The method of claim 1 , prior to the formation of the hole in the first wafer, the method further comprising providing a second wafer and bonding the first wafer to the second wafer.

9. The method of claim 8 , further comprising forming a further hole in the second wafer, the hole in the first wafer is not brought into communication with the further hole in the second wafer, or the hole in the first wafer is brought into communication with the further hole in the second wafer.

10. The method of claim 1 , wherein forming an insulating dielectric layer over a side wall of the hole comprises:
forming an insulating dielectric layer covering both the side wall and a bottom wall of the hole;
etching away a portion of the insulating dielectric layer on the bottom wall of the hole.

11. The method of claim 9 , further comprising:
providing a first insulating layer on a front side of the substrate in the first wafer and providing a second insulating layer on a front side of a substrate in the second wafer, the first insulating layer having a first metal interconnect formed therein, the second insulating layer having a second metal interconnect formed therein;
forming a first opening by etching away the insulating dielectric layer on a bottom wall of the hole in the first wafer and forming a second opening by etching away the insulating dielectric layer on a bottom wall of the further hole in the second wafer,
the conductive layer filling the first opening, electrically connecting the conductive layer in the hole and the first opening to the first metal interconnect, the conductive layer further filling the second opening, electrically connecting the conductive layer in the further hole and the second opening to the second metal interconnect.

12. A semiconductor device, comprising:
a first substrate;
a hole extending through the first substrate;
an insulating dielectric layer covering a side wall of the hole;
a conductive layer filled in the hole, wherein the insulating dielectric layer is formed outside of the conductive layer and is sandwiched between the substrate and the conductive layer, wherein at least part of the insulating dielectric layer in correspondence with the substrate is removed, forming an air gap between the conductive layer and the substrate; and
a closure layer, which closes the air gap,
wherein the air gap is formed outside of the conductive layer, and disposed in the insulating dielectric layer that is sandwiched between the substrate and the conductive layer, resulting in a significant reduction in parasitic capacitance between the conductive layer, the insulating dielectric layer and the first substrate.

13. The semiconductor device of claim 12 , wherein the insulating dielectric layer is a single-layer structure or a stack of at least two layers.

14. The semiconductor device of claim 13 , wherein in case of the insulating dielectric layer being a stack of at least two layers, a portion of any one of the at least two layers situated in correspondence with the substrate is removed so that the air gap is present in this layer.

15. The semiconductor device of claim 14 , wherein the insulating dielectric layer comprises, stacked sequentially over the side wall of the hole, a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer, and wherein the air gap is present in the silicon nitride layer in the insulating dielectric layer.

16. The semiconductor device of claim 12 , wherein in the air gap, the substrate is exposed, or the conductive layer is exposed, or both the substrate and the conductive layer are exposed.

17. The semiconductor device of claim 12 , wherein in the air gap, neither the substrate nor the conductive layer is exposed.

18. The semiconductor device of claim 12 , wherein there is no conductive layer between the air gap and the substrate.

19. The semiconductor device of claim 12 , further comprising:
a first die containing the first substrate; and
a second die bonded to the first die.

20. The semiconductor device of claim 12 , wherein there is air or vacuum in the air gap.

Assignees

• Wuhan Xinxin Semiconductor Mfg

Inventors

• Lin Fei

Classifications

• H10W20/0265

  characterised by the sidewall insulation · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0253

  comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates · CPC title