Pixel circuit and driving method thereof, and display device

Patent metadata

Field	Value
Publication number	US-12014685-B2
Application number	US-202318215227-A
Country	US
Kind code	B2
Filing date	Jun 28, 2023
Priority date	Apr 30, 2021
Publication date	Jun 18, 2024
Grant date	Jun 18, 2024

Abstract

A pixel circuit and a driving method thereof, and a display device are provided. The pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a compensation sub-circuit, and a first reset sub-circuit, and is configured to generate a driving current to control a light-emitting element to emit light, the first reset sub-circuit comprises a first transistor, the compensation sub-circuit comprises a second transistor, the first transistor and the second transistor are both polysilicon oxide thin film transistors, and an active layer type of the first transistor and an active layer type of the second transistor are different from an active layer type of a transistor comprised in at least one selected from a group consisting of the driving sub-circuit, the data writing sub-circuit, the first light-emitting control sub-circuit, and the second light-emitting control sub-circuit.

First claim

What is claimed is:

1. A pixel circuit, comprising a driving sub-circuit, a data writing sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a compensation sub-circuit, and a first reset sub-circuit, and configured to generate a driving current to control a light-emitting element to emit light,
wherein the driving sub-circuit comprises a control terminal, a first terminal, and a second terminal;
the data writing sub-circuit is electrically connected to the first terminal of the driving sub-circuit and a data signal terminal, and is configured to write a data signal of the data signal terminal into the first terminal of the driving sub-circuit in response to a signal of a first scan signal terminal;
the compensation sub-circuit is electrically connected to the second terminal of the driving sub-circuit and the control terminal of the driving sub-circuit, and is configured to perform threshold compensation on the driving sub-circuit in response to a signal of a compensation control signal terminal;
the first reset sub-circuit is electrically connected to the second terminal of the driving sub-circuit and a second voltage terminal, and is configured to write a signal of the second voltage terminal into the second terminal of the driving sub-circuit in response to a signal of a second scan signal terminal;
wherein the compensation sub-circuit comprises a second transistor, the data writing sub-circuit comprises a third transistor, the second transistor is an oxide transistor, and an active layer type of the second transistor is different from an active layer type of a transistor comprised in at least one selected from a group consisting of the driving sub-circuit, the data writing sub-circuit, the first light-emitting control sub-circuit, and the second light-emitting control sub-circuit; and
wherein a duration when the second transistor is turned on for one time is larger than a duration when the third transistor is turned on for one time.

2. The pixel circuit according to claim 1 , wherein the first reset sub-circuit comprises a first transistor, and the first transistor is an oxide transistor or a low temperature polysilicon transistor.

3. The pixel circuit according to claim 1 , further comprising a second reset sub-circuit,
wherein the second reset sub-circuit is electrically connected to a first electrode of the light-emitting element and a third voltage terminal, and is configured to write a signal of the third voltage terminal into the first electrode of the light-emitting element in response to a signal of a reset control signal terminal to reset the first electrode of the light-emitting element.

4. The pixel circuit according to claim 3 , wherein the first scan signal terminal and the reset control signal terminal are connected to an identical signal line.

5. The pixel circuit according to claim 4 , wherein in a case where the pixel circuit is in a first display mode, a turn-on frequency of the third transistor is greater than a turn-on frequency of the second transistor, and in a case where the third transistor and the second transistor are both turned on, the data signal is transmitted to the control terminal of the driving sub-circuit.

6. The pixel circuit according to claim 3 , wherein a voltage value of the signal of the third voltage terminal is greater than a voltage value of the signal of the second voltage terminal.

7. The pixel circuit according to claim 3 , wherein the second reset sub-circuit comprises a seventh transistor, a first electrode of the seventh transistor is electrically connected with the third voltage terminal, and a second electrode of the seventh transistor is electrically connected with the first electrode of the light-emitting element.

8. The pixel circuit according to claim 3 , wherein the second reset sub-circuit comprises a seventh transistor, in a case where the pixel circuit is in a first display mode, a turn-on frequency of the seventh transistor is greater than a turn-on frequency of the second transistor.

9. The pixel circuit according to claim 3 , wherein the second reset sub-circuit comprises a seventh transistor, and the duration when the second transistor is turned on for one time is larger than a duration when the seventh transistor is turned on for one time.

10. The pixel circuit according to claim 3 , wherein the first reset sub-circuit comprises a first transistor and the second reset sub-circuit comprises a seventh transistor,
a channel width of the seventh transistor ranges from 1.5 μm to 3 μm, and a channel length of the seventh transistor ranges from 2 μm to 4 μm, and
a channel width of the first transistor T 1 ranges from 1.5 μm to 3 μm, and a channel length of the first transistor ranges from 2 μm to 4 μm.

11. The pixel circuit according to claim 3 , wherein the first reset sub-circuit comprises a first transistor and the second reset sub-circuit comprises a seventh transistor,
a ratio of a channel length of the first transistor to a channel length of the seventh transistor is 1 to 2.

12. The pixel circuit according to claim 3 , wherein a voltage range of the second voltage terminal ranges from −2V to −6V, and a voltage range of the third voltage terminal ranges from −2V to −5V.

13. The pixel circuit according to claim 1 , further comprising a storage sub-circuit, wherein the storage sub-circuit comprises a first capacitor, and the driving sub-circuit comprises a fourth transistor,
the control terminal of the driving sub-circuit comprises a gate electrode of the fourth transistor, the first terminal of the driving sub-circuit comprises a first electrode of the fourth transistor, and the second terminal of the driving sub-circuit comprises a second electrode of the fourth transistor;
a gate electrode of the second transistor is electrically connected with the compensation control signal terminal, a second electrode of the second transistor is electrically connected with the second electrode of the fourth transistor, and a first electrode of the second transistor is electrically connected with the gate electrode of the fourth transistor;
a first end of the first capacitor is electrically connected with the gate electrode of the fourth transistor, and a second end of the first capacitor is electrically connected with a first voltage terminal;
a gate electrode of the third transistor is electrically connected with the first scan signal terminal, a first electrode of the third transistor is electrically connected with the data signal terminal, and a second electrode of the third transistor is electrically connected with the first electrode of the fourth transistor.

14. The pixel circuit according to claim 1 , wherein the first light-emitting control sub-circuit comprises a fifth transistor, and the second light-emitting control sub-circuit comprises a sixth transistor;
a gate electrode of the fifth transistor is electrically connected with a light-emitting signal control terminal, a first electrode of the fifth transistor is connected with a first voltage terminal, and a second electrode of the fifth transistor is electrically connected with the first terminal of the driving sub-circuit;
a gate electrode of the sixth transistor is electrically connected with the light-emitting signal control terminal, a first electrode of the sixth transistor is electrically connected with the second terminal of the driving sub-circuit, and a second electrode of the sixth transistor is electrically connected with a first electrode of the light-emitting element.

15. The pixel circuit according to claim 14 , wherein in a case

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Wang Rui
• Hu Ming
• Qiu Haijun
• Huang Weiyun
• Huang Yao
• Zeng Chao
• Qiu Yuanyou
• Li Shaoru
• Cheng Tianyi

Classifications

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title