Light-emitting diode display panel and light-emitting diode display device

US12014672B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12014672-B2
Application numberUS-202217968266-A
CountryUS
Kind codeB2
Filing dateOct 18, 2022
Priority dateMay 6, 2021
Publication dateJun 18, 2024
Grant dateJun 18, 2024

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  1. Title

    What the patent document calls the invention.

  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Disclosed are a display panel and a display device. The display panel includes a display area, a plurality of light-emitting elements located in the display area, and at least one driver circuit located in the display area; the plurality of light-emitting elements includes a plurality of light-emitting element rows extend in a first direction and arranged in a second direction, where the first direction and the second direction intersect; the at least one driver circuit includes a plurality of shift register circuits disposed in cascade and a shift register circuit of the plurality of shift register circuits is located between adjacent light-emitting element rows of the plurality of light-emitting element rows.

First claim

Opening claim text (preview).

What is claimed is: 1. A display panel, comprising a display area; wherein the display panel further comprises: a plurality of light-emitting elements, wherein the plurality of light-emitting elements are located in the display area; a plurality of light-emitting control lines, a plurality of scan lines and a plurality of data lines, wherein the plurality of scan lines and the plurality of light-emitting control lines extend along a first direction and are arranged along a second direction, and the plurality of data lines extend along the second direction and are arranged along the first direction; a plurality of driver circuits, wherein the plurality of driver circuits are located in the display area, a driver circuit of the plurality of driver circuits comprises a plurality of shift register circuits disposed in cascade, wherein the driver circuits comprise scan driver circuits and light-emitting control driver circuits; and a plurality of pixel circuits, wherein the scan driver circuits provide scan signals to the plurality of pixel circuits through the plurality of scan lines, and the light-emitting control driver circuits provide light-emitting control signals to the plurality of pixel circuits through the plurality of light-emitting control lines; wherein the light-emitting control driver circuits comprise a first light-emitting control driver circuit and a second light-emitting control driver circuit, along the first direction, a scan driver circuit is located between the first light-emitting control driver circuit and the second light-emitting control driver circuit, or the scan driver circuits comprise a first scan driver circuit and a second scan driver circuit, and along the first direction, a light-emitting control driver circuit is located between the first scan driver circuit and the second scan driver circuit. 2. The display panel of claim 1 wherein the plurality of pixel circuits are configured to drive the plurality of light-emitting elements, and the plurality of light-emitting elements do not overlap with the plurality of pixel circuits. 3. The display panel of claim 1 , A display panel, comprising a display area; wherein the display panel further comprises: a plurality of light-emitting elements, wherein the plurality of light-emitting elements are located in the display area; a plurality of scan lines and a plurality of data lines, wherein the plurality of scan lines extend along a first direction and are arranged along a second direction, and the plurality of data lines extend along the second direction and are arranged along the first direction; and a plurality of driver circuits, wherein the plurality of driver circuits are located in the display area, a driver circuit of the plurality of driver circuits comprises a plurality of shift register circuits disposed in cascade; wherein the plurality of driver circuits comprise scan driver circuits and light-emitting control driver circuits, and along the first direction, a light-emitting control driver circuit is located between adjacent two scan driver circuits or a scan driver circuit is located between adjacent two light-emitting control driver circuits; wherein the plurality of light-emitting elements do not overlap with the driver circuit. 4. The display panel of claim 1 , wherein the plurality of driver circuits comprise a scan driver circuit, the scan driver circuit comprises a plurality of scan shift register circuits disposed in cascade, the plurality of light-emitting elements comprise a plurality of light-emitting element rows, the plurality of light-emitting element rows extend in the first direction and are arranged in the second direction, and the scan shift register circuit is located between adjacent light-emitting element rows of the plurality of light-emitting element rows. 5. The display panel of claim 4 , wherein a scan shift register circuit of the plurality of scan shift register circuits comprises a first latch module, a logic module and a first buffer module and the first latch module, the logic module and the first buffer module are arranged in the first direction. 6. The display panel of claim 1 , wherein the driver circuit comprises a light-emitting control driver circuit, wherein the light-emitting control driver circuit comprises a plurality of light-emitting control shift register circuits disposed in cascade, the plurality of light-emitting elements comprise a plurality of light-emitting element rows, and a light-emitting control shift register circuit of the plurality of light-emitting control shift register circuits is located between adjacent light-emitting element rows. 7. The display panel of claim 6 , wherein the light-emitting control shift register circuit comprises a second latch module and a second buffer module, and the second latch module and the second buffer module are arranged in the first direction. 8. The display panel of claim 1 , wherein the plurality of light-emitting elements comprise a plurality of light-emitting element rows, the plurality of light-emitting element rows comprise at least one light-emitting element row group, and the at least one light-emitting element row group each comprises two light-emitting element rows disposed adjacent to each other in the second direction; and wherein the at least one light-emitting element row group is provided with two shift register circuits disposed in cascade. 9. The display panel of claim 8 , wherein the driver circuit comprises a scan driver circuit and a light-emitting control driver circuit, wherein the scan driver circuit comprises a plurality of scan shift register circuits disposed in cascade, and wherein the light-emitting control driver circuit comprises a plurality of light-emitting control shift register circuits disposed in cascade; wherein at least two light-emitting element row groups each is provided with two scan shift register circuits disposed in cascade; and wherein at least one light-emitting element row group each is provided with two light-emitting control shift register circuits disposed in cascade. 10. The display panel of claim 1 , wherein the plurality of light-emitting elements comprise a plurality of light-emitting element rows, the plurality of light-emitting element rows extend in the first direction and are arranged in the second direction, the plurality of light-emitting element rows comprise at least two light-emitting element row group, and the at least two light-emitting element row groups each comprises two light-emitting element rows disposed adjacent to each other in the second direction; and wherein at least two shift register circuits in cascade are located in different light-emitting element row groups. 11. The display panel of claim 1 , wherein the plurality of shift register circuits disposed in cascade comprises odd-numbered shift register circuits and even-numbered shift register circuits; wherein the odd-numbered shift register circuits are disposed along the second direction, and the even-numbered shift register circuits are disposed along the second direction; and wherein the odd-numbered shift register circuits and the even-numbered shift register circuits are sequentially disposed in the first direction. 12. The display panel of claim 11 , wherein a shift register circuit of the plurality of shift register circuits disposed in cascade comprises at least a latch module and a buffer module; and wherein along the first direction, a latch module of the odd-numbered shift register circuit is located on a side of a buffer module of the odd-numbered shift register circuit facing the even-numbered shift register circuits, and a latch module of the even-nu

Assignees

Inventors

Classifications

  • Arrangements to prevent high voltage or static electricity failures · CPC title

  • Layout of electrodes and connections · CPC title

  • Integration of the drivers onto the display substrate · CPC title

  • Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title

  • Details of a shift registers arranged for use in a driving circuit · CPC title

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What does patent US12014672B2 cover?
Disclosed are a display panel and a display device. The display panel includes a display area, a plurality of light-emitting elements located in the display area, and at least one driver circuit located in the display area; the plurality of light-emitting elements includes a plurality of light-emitting element rows extend in a first direction and arranged in a second direction, where the first …
Who is the assignee on this patent?
Hubei Yangtze Ind Innovation Center Of Advanced Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/32. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 18 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).