Instruction execution method and instruction execution device

Patent metadata

Field	Value
Publication number	US-12014181-B2
Application number	US-202218052909-A
Country	US
Kind code	B2
Filing date	Nov 4, 2022
Priority date	Nov 22, 2021
Publication date	Jun 18, 2024
Grant date	Jun 18, 2024

Abstract

An instruction configuration and execution method includes the following steps. A target instruction is received through an instruction cache. The target instruction is decoded by an instruction translator. It is determined whether the target instruction has the authority to read or write the model specific register in an unprivileged state. It is determined whether the model specific register index of the specific instruction corresponds to a specific model specific register, so as to order the microprocessor to perform an instruction serialization operation.

First claim

What is claimed is:

1. An instruction configuration and execution method, applicable to a microprocessor; wherein the microprocessor comprises a model specific register (MSR), and the instruction configuration and execution method comprises:
receiving a target instruction using an instruction cache; and
decoding the target instruction using an instruction translator to determine whether the target instruction has permission to read or write the model specific register in an unprivileged state, and whether a model specific register index of a specific instruction corresponds to a specific model specific register, so as to instruct the microprocessor to execute an instruction serialization operation;
wherein when the microprocessor determines that a previous instruction is completed, the microprocessor submits the target instruction and sends continuing operation information to the instruction cache, and the instruction cache receives a new target instruction.

2. The instruction configuration and execution method of claim 1 , wherein when the model specific register index corresponds to a first specific model specific register, the microprocessor executes a first instruction serialization operation, and sends a stall message to the instruction cache to stop receiving the new target instruction.

3. The instruction configuration and execution method of claim 2 , wherein the microprocessor uses the execution unit to detect whether the write operation of the previous instruction is completed, and submits the target instruction when the execution unit detects that the write operation of the previous instruction is completed.

4. The instruction configuration and execution method of claim 1 , wherein when the model specific register index corresponds to a second specific model specific register, the microprocessor executes a second instruction serialization operation, a plurality of bits of the second model specific register respectively correspond to a plurality of internal features of a second instruction, and when the second instruction serialization operation is performed, the microprocessor implements the internal features of the second instruction according to the bits of the second model specific register.

5. The instruction configuration and execution method of claim 4 , wherein the microprocessor determines whether the internal features of the second instruction are executed and determines the order in which the second instruction is executed according to the bits of the second model specific register.

6. The instruction configuration and execution method of claim 4 , wherein remaining bits of the model specific register corresponding to the model specific register index are used to adjust the order in which the internal features are executed.

7. The instruction configuration and execution method of claim 6 , wherein the remaining bits are allowed to be overwritten.

8. The instruction configuration and execution method of claim 1 , wherein:
when the model specific register index is in the address range, a read-write indication value is obtained to check the read-write permission of the target instruction; and
when the model specific register index is not in the address range, the complete set of read-write indication values of the model specific register is obtained to obtain the read-write permission of the target instruction.

9. An instruction configuration and execution device, applicable to a microprocessor, wherein the instruction configuration and execution device comprises:
a model specific register (MSR);
an instruction cache, configured to receive a target instruction; and
an instruction translator, configured to decode the target instruction to determine whether the target instruction has permission to read or write the model specific register in an unprivileged state, and whether a model specific register index of a specific instruction corresponds to a specific model specific register, so as to instruct the microprocessor to execute an instruction serialization operation;
wherein when the microprocessor determines that a previous instruction is completed, the microprocessor submits the target instruction and sends continuing operation information to the instruction cache, and the instruction cache receives a new target instruction.

10. The instruction configuration and execution device of claim 9 , wherein when the model specific register index corresponds to a first specific model specific register, the microprocessor executes a first instruction serialization operation, and sends a stall message to the instruction cache to stop receiving the new target instruction.

11. The instruction configuration and execution device of claim 10 , wherein the microprocessor detects, using the execution unit, whether the write operation of the previous instruction is completed, and submits the target instruction when the execution unit detects that the write operation of the previous instruction is completed.

12. The instruction configuration and execution device of claim 9 , wherein when the model specific register index corresponds to a second specific model specific register, the microprocessor executes a second instruction serialization operation, a plurality of bits of the second model specific register respectively correspond to a plurality of internal features of a second instruction, and when the second instruction serialization operation is performed, the microprocessor implements the internal features of the second instruction according to the bits of the second model specific register.

13. The instruction configuration and execution device of claim 12 , wherein the microprocessor determines whether the internal features of the second instruction are executed and determines the order in which the second instruction is executed according to the bits of the second model specific register.

14. The instruction configuration and execution device of claim 12 , wherein remaining bits of the model specific register corresponding to the model specific register index are used to adjust the order in which the internal features are executed.

15. The instruction configuration and execution device of claim 14 , wherein the remaining bits are allowed to be overwritten.

16. The instruction configuration and execution device of claim 9 , wherein:
when the model specific register index is in the address range, a read-write indication value is obtained to check the read-write permission of the target instruction; and
when the model specific register index is not in the address range, the complete set of read-write indication values of the model specific register is obtained to obtain the read-write permission of the target instruction.

17. An instruction execution method, applicable to a microprocessor, and an instruction execution method, applicable to a microprocessor, wherein the instruction execution method includes:
configuring a model specific register to enable read-write permission but not read and write;
decoding a target instruction using an instruction translator; and
determining whether the target instruction includes a model specific register index;
wherein when the target instruction includes the model specific register index, the target instruction instructs the microprocessor to execute other instructions before and after serialization;
wherein when the microprocessor determines that a previous instruction is completed, the microprocessor submits the target instruction and sends continuing operation information to an instruction cache, and the instruction cache receiv

Assignees

• Shanghai Zhaoxin Semiconductor Co Ltd

Inventors

• Wang Weilin
• Guan Yingbing
• Yi Lei
• Cheng Long

Classifications

• G06F9/3818

  Decoding for concurrent execution · CPC title

• G06F9/30101

  Special purpose registers · CPC title

• G06F9/30087 Primary

  Synchronisation or serialisation instructions · CPC title

• G06F12/0815

  Cache consistency protocols · CPC title

• G06F8/44

  Encoding · CPC title