Multiplier-accumulator unit element with binary weighted charge transfer capacitors

Patent metadata

Field	Value
Publication number	US-12014152-B2
Application number	US-202117334816-A
Country	US
Kind code	B2
Filing date	May 31, 2021
Priority date	May 31, 2021
Publication date	Jun 18, 2024
Grant date	Jun 18, 2024

Abstract

A Unit Element (UE) has a digital X input and a digital W input, and comprises groups of NAND gates generating complementary outputs which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The number of bits in the X input determines the number of NAND gates in a NAND-group and the number of bits in the W input determines the number of NAND groups. Each NAND-group receives one bit of the W input applied to all of the NAND gates of the NAND-group, and each unit element having the bits of X applied to each associated NAND gate input of each unit element. The NAND gate outputs are coupled through binary weighted charge transfer capacitors to a positive charge transfer line and negative charge transfer line.

First claim

We claim:

1. A Multiplier-Accumulator (MAC) Unit Element (UE) performing a bitwise multiplication of an X digital input with a W digital input and transferring a charge to a charge transfer bus comprising a positive charge transfer line and a negative charge transfer line, the MAC UE comprising:
a plurality of NAND-groups, each NAND-group receiving one of the W digital input bits, each NAND-group comprising a plurality of NAND gates, each NAND gate of a NAND-group having an input coupled to a W digital input bit and an input coupled to a unique one of the X digital input bits;
each NAND gate having a positive output and a negative output, the positive output coupled through a binary weighted charge transfer capacitor to the positive charge transfer line, the negative output coupled through a binary weighted charge transfer capacitor to the negative charge transfer line;
each binary weighted charge transfer capacitor having an associated binary weight determined by a sum of bit positions for a corresponding X digital input bit and W digital input bit.

2. The MAC UE of claim 1 where the binary weight is 2 to a power of a sum of the bit positions for a corresponding X digital input bit and a corresponding W digital input bit of a corresponding NAND gate.

3. The MAC UE of claim 1 where the bitwise multiplication results in transferring a charge proportional to a product of X and W.

4. The MAC UE of claim 1 where the X digital input comprises three bits and the W digital input comprises three bits exclusive of a sign bit.

5. The MAC UE of claim 1 where the W digital input includes a sign bit exclusively enabling a first plurality of NAND-groups or a second plurality of NAND-groups.

6. The MAC UE of claim 1 where each NAND gate has a negative output coupled through a binary weighted charge transfer capacitor to the positive charge transfer line and a positive output coupled through a binary weighted charge transfer capacitor to a respective negative charge transfer line.

7. The MAC UE of claim 1 where the positive charge transfer capacitor and the negative charge transfer capacitor each comprise nine charge transfer capacitors, each respective charge transfer capacitor having a weight of 1, 2, 4, 2, 4, 8, 4, 8, and 16.

8. The MAC UE of claim 1 where the W input includes a sign bit, the sign bit enabling or disabling NAND-groups of a MAC UE.

9. The MAC UE of claim 8 where the MAC UE comprises a positive MAC UE which is only enabled when the sign bit is positive and a negative MAC UE which is only enabled with the sign bit is negative.

10. A Multiplier-Accumulator (MAC) unit element (UE) accepting an X digital input and a W digital input accompanied by a sign bit input, the MAC UE comprising:
a charge transfer bus comprising a positive charge transfer line and a negative charge transfer line;
a positive unit element and a negative unit element;
when the sign bit input is positive, the positive unit element operative to perform a bit-by-bit NAND operation asserting an output and also a complement output, the output transferring a charge through a binary weighted charge transfer capacitor to the negative charge transfer line, the complement output transferring a charge through a binary weighted charge transfer capacitor to the positive charge transfer line;
when the sign bit input is negative, the negative unit element operative to perform a bit-by-bit NAND operation asserting an output and also a complement output, the output transferring a charge through a binary weighted charge transfer capacitor to the positive charge transfer line, the complement output transferring a charge through a binary weighted charge transfer capacitor to the negative charge transfer line.

11. The MAC UE of claim 10 where the bit-by-bit NAND operation is performed by a NAND-group, each NAND gate of the NAND-group receiving one of the W input bits, the sign bit, and one of the X input bits to generate a respective output and complement output.

12. The MAC UE of claim 10 where the charge transfer capacitors comprises nine positive charge transfer capacitors and nine negative charge transfer capacitors.

13. The MAC UE of claim 12 where the positive charge transfer capacitors and negative charge transfer capacitors each have weights 1, 2, 4, 2, 4, 8, 4, 8, and 16.

14. The MAC UE of claim 10 where the MAC UE receives a clear input causing all of the NAND outputs to be high and all of the complement outputs to be low.

15. A multiply-accumulate (MAC) unit element (UE) for coupling a multiplication result from an X digital input, a sign bit, and a W digital input as bit-wise charge values to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line;
the MAC UE comprising a positive MAC UE which is operative when the sign bit is positive and a negative MAC UE which is operative when the sign bit is negative;
the positive MAC UE comprising a plurality of NAND-groups, one NAND-group for each W digital input bit, each NAND group comprising a plurality of NAND gates, one NAND gate for each X digital input bit, each NAND gate of the NAND-group having an input coupled to one of the W digital input bits, an input coupled to a unique X digital input bit, each NAND gate generating a positive output coupled through a binary weighted charge transfer capacitor to the negative charge transfer line and a negative output coupled through a binary weighted charge transfer capacitor to the positive charge transfer line;
the negative MAC UE comprising a plurality of NAND-groups, one NAND-group for each W digital input bit, each NAND group comprising a plurality of NAND gates, one NAND gate for each X digital input bit, each NAND gate of the NAND-group having an input coupled to one of the W digital input bits, an input coupled to a unique X digital input bit, each NAND gate generating a positive output coupled through a binary weighted charge transfer capacitor to the positive charge transfer line and a negative output coupled through a binary weighted charge transfer capacitor to the negative charge transfer line.

16. The MAC UE of claim 15 where the plurality of positive charge transfer capacitors and the plurality of negative charge transfer capacitors each have relative weights 1, 2, 4, 2, 4, 8, 4, 8, and 16.

17. The MAC UE of claim 15 where each NAND group includes a clear input.

18. The MAC UE of claim 17 where the clear input causes the positive MAC UE and negative MAC UE to assert a positive output high and negative output low.

19. The MAC UE of claim 15 where the X digital input comprises three bits and the W digital input comprises three bits.

Assignees

• Redpine Signals Inc
• Ceremorphic Inc

Inventors

• Kraemer Martin
• Boesch Ryan
• Xiong Wei

Classifications

• H03M3/04

  Differential modulation with several bits {, e.g. differential pulse code modulation [DPCM] (H03M3/30 takes precedence)} · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03M1/466

  using switched capacitors · CPC title

• G06F7/5443 Primary

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title