Multi-port queueing cache and data processing system including the same

Patent metadata

Field	Value
Publication number	US-12013786-B2
Application number	US-202218072929-A
Country	US
Kind code	B2
Filing date	Dec 1, 2022
Priority date	Dec 22, 2021
Publication date	Jun 18, 2024
Grant date	Jun 18, 2024

Abstract

In some embodiments, a multi-port queueing cache includes a plurality of first ports, a plurality of second ports, a plurality of request handlers respectively coupled to the plurality of first ports, a cache storage unit coupled to the plurality of second ports, a reserve interface configured to exchange at least one address and at least one reserved cache line number, and a request interface configured to exchange the at least one reserved cache line number and at least one data. The reserve interface and the request interface are disposed between the plurality of request handlers and the cache storage unit. The cache storage unit includes a plurality of cache lines configured to store the plurality of data. The cache storage unit is configured to output a portion of the plurality of addresses, and receive a portion of the plurality of data corresponding to the portion of the plurality of addresses.

First claim

What is claimed is:

1. A multi-port queueing cache, comprising:
a plurality of first ports and a plurality of second ports;
a plurality of request handlers respectively coupled to the plurality of first ports, the plurality of request handlers being configured to receive a plurality of addresses through the plurality of first ports, and to output a plurality of data corresponding to the plurality of addresses through the plurality of first ports;
a cache storage coupled to the plurality of second ports, the cache storage including a plurality of cache lines configured to store the plurality of data, the cache storage being configured to output at least a portion of the plurality of addresses through the plurality of second ports, and to receive at least a portion of the plurality of data corresponding to the at least a portion of the plurality of addresses through the plurality of second ports;
a reserve interface configured to exchange at least one address and at least one reserved cache line number; and
a request interface configured to exchange the at least one reserved cache line number and at least one data,
wherein the reserve interface and the request interface are disposed between each of the plurality of request handlers and the cache storage.

2. The multi-port queueing cache of claim 1 , wherein the cache storage includes:
a plurality of cache banks coupled to the plurality of second ports, each of the plurality of cache banks including at least one of the plurality of cache lines.

3. The multi-port queueing cache of claim 2 , wherein a first reserve interface and a first request interface are disposed between a first request handler of the plurality of request handlers and a first cache bank of the plurality of cache banks.

4. The multi-port queueing cache of claim 3 , wherein:
the first request handler is configured to sequentially receive first to N-th addresses through a corresponding first port of the plurality of first ports, and to sequentially transfer the first to N-th addresses that are received through the corresponding first port to the first cache bank through the first reserve interface, where N is an integer greater than one, and
in response to first data corresponding to the first address being not stored in the first cache bank, the first cache bank is configured to:
allocate the first address to a first cache line;
output the first address through a corresponding second port of the plurality of second ports;
transfer a cache line number of the first cache line to the first request handler through the first reserve interface;
receive the first data through the second port; and
store the first data received through the second port into the first cache line.

5. The multi-port queueing cache of claim 4 , wherein:
the first request handler is configured to transfer the cache line number of the first cache line received through the first reserve interface to the first cache bank through the first request interface,
the first cache bank is configured to transfer the first data stored in the first cache line to the first request handler through the first request interface, and
the first request handler is configured to output the first data that is received through the first request interface through the first port.

6. The multi-port queueing cache of claim 5 , wherein the first cache line includes:
a first tag part that includes a plurality of flip-flops and is configured to store a part of the first address;
a first reference count part includes another plurality of flip-flops and is configured to store a first reference count value; and
a first data storage part that includes a static random access memory (SRAM) and is configured to store the first data.

7. The multi-port queueing cache of claim 6 , wherein:
before the first address is allocated to the first cache line, the first reference count value is zero,
after the first address is allocated to the first cache line and before the cache line number of the first cache line is transferred to the first request handler, the first reference count value is increased, and
before the first data that is stored in the first cache line is transferred to the first request handler, the first reference count value is decreased.

8. The multi-port queueing cache of claim 6 , wherein the first cache line includes:
a first update part configured to update the first reference count value based on the first reference count value that is stored in the first reference count part and inputs from the plurality of first ports.

9. The multi-port queueing cache of claim 4 , wherein the first request handler includes:
a first request queue configured to queue the cache line number of the first cache line received through the first reserve interface, and to output the cache line number of the first cache line through the first request interface.

10. The multi-port queueing cache of claim 4 , wherein, in response to second data corresponding to a second address being stored in the first cache bank, the first cache bank is configured to transfer a cache line number of a second cache line to which the second address is allocated and that stores the second data to the first request handler through the first reserve interface, without outputting the second address through the second port and without receiving the second data through the second port.

11. The multi-port queueing cache of claim 2 , further comprising:
a reserve bus for the reserve interface between the plurality of request handlers and the plurality of cache banks; and
a request bus for the request interface between the plurality of request handlers and the plurality of cache banks.

12. The multi-port queueing cache of claim 1 , wherein the cache storage includes:
a cache register file coupled to the plurality of second ports, the cache register file including the plurality of cache lines.

13. The multi-port queueing cache of claim 12 , wherein each of the plurality of cache lines includes:
a tag part that includes a first plurality of flip-flops and is configured to store a part of one of the plurality of addresses;
a reference count part that includes a second plurality of flip-flops and is configured to store a reference count value; and
a data storage part that includes a third plurality of flip-flops and is configured to store one of the plurality of data.

14. A data processing system comprising:
a data processing device;
a memory device configured to store a plurality of data used for calculations performed by the data processing device; and
a first multi-port queueing cache between the data processing device and the memory device,
wherein the first multi-port queueing cache includes:
a plurality of first ports and a plurality of second ports;
a plurality of first request handlers configured to receive a plurality of first addresses through the plurality of first ports, and to output a plurality of first data corresponding to the plurality of first addresses through the plurality of first ports;
a first cache storage including a plurality of first cache lines configured to store the plurality of first data, the first cache storage being configured to output at least a portion of the plurality of first addresses through the plurality of second ports, and to receive at least a portion of the plurality of first data corresponding to the at least a portion of the plurality of first addresses through the plurality of second ports;
a first reserve interface configured to exchange at least one address and at least one reserved cache line number; and
a first request interfac

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Heonsoo
• Hong Byungchul
• Park Junseok
• Chung Jaehun

Classifications

• G06F12/0261

  using reference counting · CPC title

• G06F9/3816

  Instruction alignment, e.g. cache line crossing · CPC title

• G06F12/0646

  Configuration or reconfiguration · CPC title

• G06F2212/1008

  Correctness of operation, e.g. memory ordering · CPC title

• G06F12/0864

  using pseudo-associative means, e.g. set-associative or hashing · CPC title