Integrated current sensor with magnetic flux concentrators

Patent metadata

Field	Value
Publication number	US-12013419-B2
Application number	US-202217871873-A
Country	US
Kind code	B2
Filing date	Jul 22, 2022
Priority date	Jul 17, 2020
Publication date	Jun 18, 2024
Grant date	Jun 18, 2024

Abstract

In one example, circuitry is formed in a semiconductor die. A magnetic concentrator is formed on a surface of the semiconductor die and over the circuitry. An isolation spacer is placed on a lead frame. The semiconductor die is placed on the isolation spacer, and the magnetic concentrator is aligned to overlap the lead frame. Electrical interconnects are formed between the semiconductor die and the lead frame.

First claim

What is claimed is:

1. A method comprising:
forming circuitry in a semiconductor die;
forming a magnetic concentrator on a surface of the semiconductor die and over the circuitry;
placing an isolation spacer on a lead frame;
placing the semiconductor die on the isolation spacer, including aligning the magnetic concentrator to overlap the lead frame; and
forming electrical interconnects between the semiconductor die and the lead frame.

2. The method of claim 1 , wherein forming the magnetic concentrator includes: forming the magnetic concentrator on the surface of the semiconductor die before singulation.

3. The method of claim 2 , wherein the circuitry includes a Hall effect sensor, and the method further comprises:
establishing a location of the magnetic concentrator via masking the semiconductor die; and
forming the magnetic concentrator at the established location.

4. The method of claim 3 , wherein establishing the location of the magnetic concentrator includes: aligning between the magnetic concentrator and the Hall effect sensor.

5. The method of claim 3 , wherein:
the magnetic concentrator is a first magnetic concentrator; and
the method comprises:
forming a second magnetic concentrator on the surface of the semiconductor die; and
aligning the first and second magnetic concentrators to overlap a space therebetween with the Hall effect sensor.

6. The method of claim 3 , wherein:
the Hall effect sensor is a first Hall effect sensor;
the circuitry includes a second Hall effect sensor;
the magnetic concentrator has opposite first and second edges; and
the method comprises:
aligning the first edge of the magnetic concentrator to overlap the first Hall effect sensor; and
aligning the second edge of the magnetic concentrator to overlap the second Hall effect sensor.

7. The method of claim 6 , wherein:
the circuitry includes third and fourth Hall effect sensors;
the magnetic concentrator is a first magnetic concentrator;
the method comprises:
forming a second magnetic concentrator on the surface of the semiconductor die, the second magnetic concentrator having opposite third and fourth edges; and
aligning the second magnetic concentrator to overlap the third and fourth edges of the second magnetic concentrator to the respective third and fourth Hall effect sensors.

8. The method of claim 7 , wherein:
the lead frame includes a conductor having a current input leg and a current output leg; and
the method comprises:
aligning the first magnetic concentrator to overlap the current input leg; and
aligning the second magnetic concentrator to overlap the current output leg.

9. The method of claim 8 , wherein the conductor has a bent segment electrically coupled between the current input and output segments.

10. The method of claim 8 , wherein the conductor has a U shape.

11. The method of claim 7 , wherein the circuitry includes a summation circuit coupled to the first through fourth Hall effect sensors.

12. The method of claim 1 , wherein forming the magnetic concentrator includes: electroplating a metal layer on the surface of the semiconductor die.

13. The method of claim 12 , wherein forming the magnetic concentrator includes: electroplating the metal layer on the surface of the semiconductor die before singulation.

14. The method of claim 1 , wherein the isolation spacer includes at least one of: a glass dielectric material, a polymer-based dielectric material, or a silicon-based dielectric material.

15. The method of claim 1 , further comprising: bonding the isolation spacer to the lead frame using an adhesive.

16. The method of claim 15 , wherein the adhesive includes an epoxy adhesive.

17. The method of claim 15 , wherein the surface is a first surface, and the isolation spacer is bonded to a second surface of the semiconductor die opposite to the first surface.

18. The method of claim 17 , wherein the isolation spacer is bonded to the second surface of the semiconductor die after singulation.

19. The method of claim 1 , wherein the electrical interconnects include bond wires.

20. The method of claim 1 , further comprising encapsulating the lead frame, the isolation spacer, and the semiconductor die with an encapsulation compound.

Assignees

• Texas Instruments Inc

Inventors

• Lee Dok Won
• Bito Jo
• Green Keith Ryan

Classifications

• H10W70/458

  of insulating layers on leadframes · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10N59/00

  Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00 (MRAM devices H10B61/00) · CPC title