Directed self-assembly structures and techniques

Patent metadata

Field	Value
Publication number	US-12012473-B2
Application number	US-202017032517-A
Country	US
Kind code	B2
Filing date	Sep 25, 2020
Priority date	Jun 2, 2020
Publication date	Jun 18, 2024
Grant date	Jun 18, 2024

Abstract

Disclosed herein are structures and techniques utilizing directed self-assembly for microelectronic device fabrication. For example, a microelectronic structure may include a patterned region including a first conductive line and a second conductive line, wherein the second conductive line is adjacent to the first conductive line; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the patterned region.

First claim

The invention claimed is:

1. A microelectronic structure, comprising:
a patterned region including a first conductive line and a second conductive line, wherein the first conductive line and the second conductive line have a pitch that is less than 30 nanometers, the first conductive line has a line edge roughness that is less than 1.2 nanometers, and the second conductive line has a line edge roughness that is less than 1.2 nanometers; and
an unpatterned region having an unordered lamellar pattern, wherein the unpatterned region is adjacent to the patterned region.

2. The microelectronic structure of claim 1 , wherein the microelectronic structure further includes pitch-division artifacts proximate to the patterned region.

3. The microelectronic structure of claim 1 , wherein the patterned region is a first patterned region, the microelectronic structure further includes a second patterned region including a first conductive line and a second conductive line, wherein the second conductive line of the second patterned region is adjacent to the first conductive line of the second patterned region, the first conductive line of the second patterned region and the second conductive line of the second patterned region have a pitch that is greater than 24 nanometers.

4. The microelectronic structure of claim 3 , wherein the first conductive line of the second patterned region has a line edge roughness that is greater than 1.2 nanometers, and the second conductive line has a line edge roughness that is greater than 1.2 nanometers.

5. The microelectronic structure of claim 3 , wherein the first conductive line of the second patterned region has a line width roughness and a line edge roughness, and the line width roughness is equal to the line edge roughness multiplied by a square root of 2.

6. The microelectronic structure of claim 3 , wherein the second patterned region is coplanar with the first patterned region.

7. The microelectronic structure of claim 3 , wherein the second patterned region is in a same layer of a metallization stack as the first patterned region.

8. The microelectronic structure of claim 1 , wherein the first conductive line has a line width roughness, and the line width roughness of the first conductive line is not equal to the line edge roughness of the first conductive line multiplied by a square root of 2.

9. The microelectronic structure of claim 1 , wherein the patterned region includes a third conductive line and a fourth conductive line, the third conductive line is between the second conductive line and the fourth conductive line, the third conductive line has a line edge roughness greater than 1.2 nanometers, and the fourth conductive line has a line edge roughness less than 1.2 nanometers.

10. The microelectronic structure of claim 1 , wherein the unpatterned region includes a block copolymer.

11. A microelectronic structure, comprising:
a patterned region including a first conductive line and a second conductive line, wherein the second conductive line is adjacent to the first conductive line; and
an unpatterned region having an unordered lamellar pattern, wherein the unpatterned region is coplanar with the patterned region.

12. The microelectronic structure of claim 11 , wherein the first conductive line includes a conductive material, and the unpatterned region includes a material having a same material composition as the conductive material.

13. The microelectronic structure of claim 11 , wherein the patterned region includes a dielectric material, and the unpatterned region includes a material having a same material composition as the dielectric material.

14. The microelectronic structure of claim 11 , wherein a spacing between the first conductive line and the second conductive line is less than 15 nanometers.

15. The microelectronic structure of claim 11 , wherein the microelectronic structure further includes a device layer, and the patterned region is included in an interconnect layer above or below the device layer.

16. The microelectronic structure of claim 11 , wherein the unpatterned region is under a guard ring of the microelectronic structure.

17. The microelectronic structure of claim 16 , wherein the first conductive line and the second conductive line are not under the guard ring.

18. The microelectronic structure of claim 11 , wherein the unpatterned region is in a frame of a die of the microelectronic structure.

19. The microelectronic structure of claim 11 , wherein the first conductive line and the second conductive line are outside of a frame of a die of the microelectronic structure.

20. The microelectronic structure of claim 11 , wherein the unpatterned region includes a block copolymer.

Assignees

• Intel Corp

Inventors

• Blackwell James Munro
• Bristol Robert L
• Chen Xuanxuan
• Doyle Lauren Elizabeth
• Gstrein Florian
• Han Eungnak
• Holybee Brandon Jay
• Krysak Marie
• Mahdi Tayseer
• Schenker Richard E
• Singh Gurpreet
• Walker Emily Susan

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/089 Primary

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title