Monitor circuitry for power management and transistor aging tracking

Patent metadata

Field	Value
Publication number	US-12009827-B2
Application number	US-202217698844-A
Country	US
Kind code	B2
Filing date	Mar 18, 2022
Priority date	Jun 26, 2020
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node.

First claim

What is claimed is:

1. An apparatus comprising:
a first circuit on a die; and
a delay locked loop coupled to the first circuit, the delay locked loop including a first circuit path on the die, the first circuit path including a phase frequency detector having a first input node to receive a first signal, and a circuit node to provide a voltage based on a comparison between the first signal at the first input node of the phase frequency detector and a second signal at a second input node of the phase frequency detector;
a delay line included in the delay locked loop, the delay line including an input node to receive the first signal and an output node to provide the second signal having a frequency based on a frequency of the first signal, the delay line including a second circuit coupled to the circuit node, the second circuit including a replica of the first circuit;
a second circuit path included in the delay locked loop and coupled between the delay line and the second input node of the phase frequency detector; and
an analog-to-digital converter coupled to the circuit node.

2. The apparatus of claim 1 , wherein the first circuit includes a logic gate and the second circuit includes a replica of the logic gate.

3. The apparatus of claim 1 , wherein the second circuit includes a transistor, the transistor having a non-gate terminal coupled to the circuit node.

4. The apparatus of claim 1 , wherein the first path includes a charge pump coupled to the phase frequency detector.

5. The apparatus of claim 4 , wherein the first path includes a filter coupled to the charge pump.

6. The apparatus of claim 5 , wherein the first path includes a transistor having a gate coupled to an output of the filter.

7. The apparatus of claim 6 , wherein the first path includes a first additional transistor coupled between the transistor and a supply node, and a second additional transistor coupled between the supply node and the circuit node.

8. The apparatus of claim 1 , further comprising a third circuit path included in the delay locked loop, the third circuit including a current mirror coupled to the circuit node.

9. An apparatus comprising:
a processor including a processing circuitry and a delay locked loop coupled to the processing circuitry, the processing circuitry including a logic circuit path, the logic circuit path including a first circuit coupled to the delay locked loop, the delay locked loop including:
a first circuit path including a phase frequency detector having a first input node to receive a first signal, and a circuit node to provide a voltage based on a comparison between the first signal at the first input node of the phase frequency detector and a second signal at a second input node of the phase frequency detector;
a delay line including an input node to receive the first signal and an output node to provide the second signal having a frequency based on a frequency of the first signal, the delay line including a second circuit coupled to the circuit node, the second circuit including a replica of the first circuit; and
a second circuit path coupled between the delay line and the second input node of the phase frequency detector.

10. The apparatus of claim 9 , further comprising an analog-to-digital converter coupled to the circuit node.

11. The apparatus of claim 9 , further comprising a connector coupled to the processor, the connector conforming with one of Universal Serial Bus (USB), High-Definition Multimedia Interface (HDMI), Thunderbolt, Peripheral Component Interconnect Express (PCIe), and Ethernet specifications.

Assignees

• Intel Corp

Inventors

• Shen Kuan-Yueh
• Kurd Nasser A
• Fallin John

Classifications

• H03L7/189

  comprising a D/A converter for generating a coarse tuning voltage · CPC title

• H01R13/665

  with built-in electronic circuit (H01R13/70, H01R13/719 take precedence) · CPC title

• H01R2201/06

  for computer periphery · CPC title

• H03L7/0893

  the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop · CPC title

• H03L7/1075

  by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth (H03L7/1072 takes precedence) · CPC title