Electronic device with frequency dithering

Patent metadata

Field	Value
Publication number	US-12009760-B2
Application number	US-202318341474-A
Country	US
Kind code	B2
Filing date	Jun 26, 2023
Priority date	Aug 30, 2022
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

An electronic device may include an inverter. The inverter may convert direct current (DC) power to alternating current (AC) power. The inverter may use a clock signal at a given frequency to output corresponding alternating current signals at the given frequency. The inverter may receive a dithered clock signal that is frequency dithered using a modulating signal. The dithered clock signal may have at least three different frequency levels during a repeated cycle of the modulating signal. The at least three different frequency levels may include a fundamental frequency, a first frequency that is lower than the fundamental frequency, and a second frequency that is higher than the fundamental frequency. The dithered clock signal may be, during the repeated cycle of the modulating signal, at the fundamental frequency for fewer total periods than at the first frequency and for fewer total periods than at the second frequency.

First claim

What is claimed is:

1. Control circuitry for a wireless power transmitter comprising:
inverter drive circuitry configured to be coupled to a wireless power transmitting coil of the wireless power transmitter, the inverter drive circuitry being further configured to receive a dithered clock signal and output corresponding alternating current signals; and
clock modulating circuitry configured to obtain the dithered clock signal using a modulating signal and a clock signal, wherein:
the dithered clock signal has at least three different frequency levels during a repeated cycle of the modulating signal;
the at least three different frequency levels include a fundamental frequency, a first frequency that is lower than the fundamental frequency, and a second frequency that is higher than the fundamental frequency; and
the dithered clock signal is, during the repeated cycle of the modulating signal, at the fundamental frequency for fewer total periods than at the first frequency and for fewer total periods than at the second frequency.

2. The control circuitry of claim 1 , wherein the dithered clock signal is at each frequency level for a respective duration of time before progressing to the subsequent frequency level and wherein the durations of time differ for at least two of the different frequency levels.

3. The control circuitry of claim 2 , wherein the durations of time for the at least two of the different frequency levels include different numbers of periods.

4. The control circuitry of claim 2 , wherein the durations of time for the frequency levels increase with increasing difference relative to the fundamental frequency.

5. The control circuitry of claim 1 , wherein the at least three different frequency levels comprise at least five different frequency levels.

6. The control circuitry of claim 5 , wherein the at least five different frequency levels comprise a third frequency that is between the first frequency and the fundamental frequency and a fourth frequency that is between the second frequency and the fundamental frequency.

7. The control circuitry of claim 6 , wherein the dithered clock signal is, during the repeated cycle of the modulating signal, at the fundamental frequency for fewer total periods than at the third frequency and for fewer total periods than at the fourth frequency.

8. The control circuitry of claim 7 , wherein the dithered clock signal is, during the repeated cycle of the modulating signal, at the first frequency for fewer total periods than at the third frequency.

9. The control circuitry of claim 7 , wherein the dithered clock signal is, during the repeated cycle of the modulating signal, at the second frequency for fewer total periods than at the fourth frequency.

10. The control circuitry of claim 6 , wherein the dithered clock signal is, during the repeated cycle of the modulating signal, at the first frequency for three periods, then at the third frequency for two periods, then at the fundamental frequency for one period, then at the fourth frequency for two periods, then at the second frequency for three periods, then at the fourth frequency for two periods, then at the fundamental frequency for one period, and then at the third frequency for two periods.

11. The control circuitry of claim 6 , wherein the first frequency is 1.702 MHz, the third frequency is 1.739 MHz, the fundamental frequency is 1.778 MHz, the fourth frequency is 1.818 MHz, and the second frequency is 1.860 MHz.

12. The control circuitry of claim 6 , wherein the repeated cycle of the modulating signal includes 16 periods of the dithered clock signal.

13. Control circuitry for a wireless power transmitter comprising:
inverter drive circuitry configured to be coupled to a wireless power transmitting coil of the wireless power transmitter, the inverter drive circuitry being further configured to receive a dithered clock signal and output corresponding alternating current signals; and
clock modulating circuitry configured to obtain the dithered clock signal using a modulating signal and a clock signal, wherein the modulating signal comprises, during a repeated cycle:
a first level that causes the dithered clock signal to have a fundamental frequency;
a second level that causes a decrease in frequency for the dithered clock signal relative to the fundamental frequency; and
a third level that causes an increase in frequency for the dithered clock signal relative to the fundamental frequency, wherein the modulating signal is, during the repeated cycle, at the first level for fewer total periods than at the second level and for fewer total periods than at the third level.

14. The control circuitry defined in claim 13 , wherein the modulating signal is at each level for a respective duration of time before progressing to the subsequent level and wherein the durations of time differ for at least two of the different levels.

15. The control circuitry defined in claim 14 , wherein the durations of time for the at least two of the different levels include different numbers of periods for the dithered clock signal.

16. The control circuitry defined in claim 14 , wherein the durations of time for the levels increase with increasing change in frequency relative to the fundamental frequency caused for the dithered clock signal.

17. The control circuitry defined in claim 13 , wherein the increase in frequency is a first increase in frequency, wherein the decrease in frequency is a first decrease in frequency, wherein the modulating signal comprises a fourth level that causes a second decrease in frequency for the dithered clock signal relative to the fundamental frequency that is less than the first decrease in frequency, and wherein the modulating signal comprises a fifth level that causes a second increase in frequency for the dithered clock signal relative to the fundamental frequency that is less than the first increase in frequency.

18. The control circuitry defined in claim 17 , wherein the modulating signal is, during the repeated cycle, at the second level for three periods, then at the fourth level for two periods, then at the first level for one period, then at the fifth level for two periods, then at the third level for three periods, then at the fifth level for two periods, then at the first level for one period, and then at the fourth level for two periods.

19. Control circuitry for a wireless power transmitter comprising:
inverter drive circuitry configured to be coupled to a wireless power transmitting coil of the wireless power transmitter, the inverter drive circuitry being further configured to receive a modified clock signal and output corresponding alternating current signals; and
clock modulating circuitry configured to obtain the modified clock signal using a modulating signal and a clock signal, wherein:
the modified clock signal has at least three different frequency levels during a repeated cycle of the modulating signal;
the at least three different frequency levels include a fundamental frequency, a first frequency that is lower than the fundamental frequency, and a second frequency that is higher than the fundamental frequency; and
the modified clock signal is, during the repeated cycle of the modulating signal, at the fundamental frequency for fewer total periods than at the first frequency and for fewer total periods than at the second frequency.

20. The control circuitry of claim 19 , wherein the modified clock signal is at each frequency level for a respective duration of time before progre

Assignees

• Apple Inc

Inventors

• Patole Sujeet Milind
• Lam Cheung-Wei
• Mahmoud Mahmoud N

Classifications

• H02M1/0041

  Control circuits in which a clock signal is selectively enabled or disabled · CPC title

• H02M7/529

  using digital control · CPC title

• H02M1/12

  Arrangements for reducing harmonics from AC input or output · CPC title

• H02M7/537

  using semiconductor devices only, e.g. single switched pulse inverters · CPC title

• H02M7/4803 Primary

  with means for reducing DC component from AC output voltage · CPC title