Header and package with integrated cooler for electronic components

Patent metadata

Field	Value
Publication number	US-12009634-B2
Application number	US-202117190860-A
Country	US
Kind code	B2
Filing date	Mar 3, 2021
Priority date	Mar 4, 2020
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

A header for an electronic component including a base body, a thermoelectric cooler, a carrier and first and second conductor track arrangements. The thermoelectric cooler is thermally attached to the base body. The carrier is coupled to the thermoelectric cooler and is cooled thereby. The first and second conductor track arrangements each have a signal conductor, at least one grounding conductor and an end. The second conductor track arrangement is on the carrier and connected to the electronic component. The first and second conductor track arrangements are separated by a gap that is bridged by bonding wire connections electrically connecting the first and second signal conductors and electrically connecting the two grounding conductors, the ends facing each other across the gap, at least one of the ends having a capacitive structural feature that increases the capacitance of the first and/or the second conductor track arrangement.

First claim

What is claimed is:

1. A header for an electronic component, comprising:
a base body having a plurality of electrical feedthroughs, the feedthroughs each having an opening that is sealed by an insulating material through which at least one feedthrough conductor extends, the at least one feedthrough conductor being electrically insulated from the base body;
a thermoelectric cooler attached to the base body, the thermoelectric cooler being thermally attached to the base body with waste heat generated by the thermoelectric cooler during operation being conducted to the base body;
a carrier for an electronic device coupled to the thermoelectric cooler, the carrier being cooled by the thermoelectric cooler;
a first conductor track arrangement including:
a first signal conductor connected to the feedthrough conductor; and
at least one grounding conductor; and

a second conductor track arrangement on the carrier, the second conductor track arrangement being connectable to the electronic device and, the second conductor track arrangement including:
a second signal conductor; and
at least one grounding conductor, the first and second conductor track arrangements being separated by a gap, the gap being bridged by bonding wire connections electrically connecting the first signal conductor to the second signal conductor and electrically connecting the two grounding conductors, the first and second conductor track arrangements each having an end, the ends facing each other, at least one of the ends of the first and second conductor track arrangements facing each other at the gap having a capacitive structural feature that adds electrical capacitance per unit length of the first and/or the second conductor track arrangement in an area of the capacitive structural feature,

wherein the capacitive structural feature includes at least one of an enlarged portion of the first and/or the second signal conductor at the ends of the conductor track arrangement, a dielectric body, a conductive bridge, and a reduced spacing between the grounding conductor and the signal conductor at the end of the first and/or the second conductor track arrangement.

2. The header of claim 1 , wherein the enlarged portion has a trapezoidal shape, the first and/or the second signal conductor widens by at least a factor of 1.5, the width of spacing between the grounding conductor and the signal conductor of the first and/or second conductor track arrangements changes by a factor of no more than 1.5 in the vicinity of the enlarged portion with the width being measured perpendicular to the longitudinal extension of the first or the second signal conductor, and the impedance increases by less than 5 ohms in the area between the capacitive structural features.

3. The header of claim 1 , wherein the first and/or the second conductor track arrangements is a coplanar waveguide.

4. The header of claim 1 , wherein the ends of the conductor track arrangements have capacitive structural features that include at least one of:
the capacitive structural features having a ratio of capacitances in a range from 0.5 to 2;
the capacitive features and the bonding wire connections have an impedance in a range from 20 Ohms to 80 Ohms;
a ratio L1/(C1+C2) has a value in a range of 1000 Ohm 2 to 5000 Ohm 2 where C1 and C2 denote the capacitances of the capacitive structural features on each of the ends of the conductor track arrangements and L1 denotes an inductance of the bonding wire connections.

5. The header of claim 1 , wherein the electronic device is mounted on a submount which includes the second conductor track arrangement.

6. The header of claim 1 , further comprising a pedestal on which the first conductor track arrangement is disposed, the pedestal being separated from the carrier for the electronic device by the gap.

7. The header of claim 6 , further comprising a circuit board, the first conductor track arrangement being disposed on the circuit board, the circuit board being mounted to the pedestal.

8. The header of claim 7 , further comprising at least one of a back-side electrode in the form of a conductive layer disposed on a side of the printed circuit board opposite the first conductor track arrangement with the at least one grounding conductor of the first conductor track arrangement connected to the back-side electrode through at least one conductive connections, the at least one grounding conductor being electrically connected to the pedestal, the signal conductor of the first conductor track arrangement changing its course by at least 45° from a direction collinear with the feedthrough conductor to which the first signal conductor is connected to a direction towards the electronic device, and the circuit board having two opposite end edges and two opposite side edges adjoining thereto with one of the end edges facing the base body and the gap being defined along one of the side edges.

9. The header of claim 1 , wherein the electronic device is an electro-optical converter in the form of a laser diode.

10. The header of claim 1 , further comprising at least one of the following features:
the at least one grounding conductor of the first conductor track arrangement extending beyond the center of a solder connection of the feedthrough conductor to the first signal line as seen opposite to the direction of the first signal line;
the gap having a width of at least 0.1 mm;
the spacing between the opposing conductor tracks of the two conductor track arrangements to be connected being at least 0.12 mm;
the bonding wire of the bonding wire connections having a length of at least 0.2 mm; and
the bonding wire of the bonding wire connections having an inductance in the range of 50 pH to 800 pH.

11. An electronic component, comprising a package, and a header as claimed in claim 1 , the package being coupled to the header.

Assignees

• Schott Ag

Inventors

• Krause Andreas
• Ping Amy Soon Li
• Wai Li Ong
• Droegemüller Karsten
• Aowudomsuk Artit

Classifications

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W40/28

  comprising Peltier coolers · CPC title

• H10W76/132

  having other interconnections through an insulated passage in the conductive base · CPC title

• H05K1/142

  Arrangements of planar printed circuit boards in the same plane, e.g. auxiliary printed circuit insert mounted in a main printed circuit · CPC title