Automatic central processing unit (CPU) usage optimization

Patent metadata

Field	Value
Publication number	US-12008401-B2
Application number	US-201916723427-A
Country	US
Kind code	B2
Filing date	Dec 20, 2019
Priority date	Dec 20, 2019
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

Automatic central processing unit (CPU) usage optimization includes: monitoring performance activity of a workload comprising a plurality of threads; and modifying a resource allocation of a plurality of cores for the plurality of threads based on the performance activity.

First claim

What is claimed is:

1. A method of automatic central processing unit (CPU) usage optimization, the CPU including a plurality of cores, the method comprising:
modifying a resource allocation of the plurality of cores for a plurality of threads based on performance activity of a workload comprising the plurality of threads; and
storing data, associated with the workload, indicating the modified resource allocation of the plurality of cores of the CPU, wherein the data indicating the modified resource allocation of the plurality of cores of the CPU is loaded upon a request for execution of the workload and the modified resource allocation is applied to the plurality of cores after the data is loaded.

2. The method of claim 1 , further comprising:
identifying, based on the performance activity, a first thread of the plurality of threads and a second thread of the plurality of threads related to the first thread;
wherein modifying the resource allocation comprises modifying a core assignment to reduce a physical distance between a first core of the plurality of cores assigned the first thread and a second core of the plurality of cores assigned the second thread.

3. The method of claim 2 , wherein the first core and the second core are located within a same compute core complex (CCX), a same core complex die (CCD), a same socket, a same non-uniform memory access (NUMA) domain, and/or a same compute node.

4. The method of claim 1 , further comprising:
identifying, based on a degree of cache misses indicated in the performance activity, a first thread of the plurality of threads and a second thread of the plurality of threads assigned to a same core of the plurality of cores;
wherein modifying the resource allocation comprises assigning one or more of the first thread and the second thread to different cores of the plurality of cores.

5. The method of claim 1 , further comprising:
monitoring, after modifying the resource allocation, additional performance activity; and
determining, based on the additional performance activity, whether to undo a modification to the resource allocation.

6. The method of claim 1 , wherein modifying the resource allocation comprises modifying, for one or more cores of the plurality of cores, one or more thresholds based on the thread each respective core of the one or more cores is executing, wherein the one or more thresholds comprise a package power tracking (PPT) threshold, a thermal design current (TDC) threshold, an electrical design current (EDC) threshold, or a Reliability Limit comprising a threshold amount of time a core can safely spend at a voltage/temperature pair.

7. The method of claim 1 , wherein the data is stored in remote memory.

8. An apparatus for automatic central processing unit (CPU) usage optimization, the apparatus comprising:
a CPU including a plurality of cores; and
memory operatively coupled to the CPU, stored within memory computer program instructions executed to:
modify a resource allocation of the plurality of cores for a plurality of threads based on performance activity of a workload comprising the plurality of threads; and
store data, associated with the workload, indicating the modified resource allocation of the plurality of cores of the CPU, wherein the data indicating the modified resource allocation of the plurality of cores of the CPU is loaded upon a request for execution of the workload and the modified resource allocation is applied to the plurality of cores after the data is loaded.

9. The apparatus of claim 8 , further comprising computer program instructions executed to:
identify, based on the performance activity, a first thread of the plurality of threads and a second thread of the plurality of threads related to the first thread;
wherein modifying the resource allocation comprises modifying a core assignment to reduce a physical distance between a first core of the plurality of cores assigned the first thread and a second core of the plurality of cores assigned the second thread.

10. The apparatus of claim 9 , wherein the first core and the second core are located within a same compute core complex (CCX), a same core complex die (CCD), a same socket, a same non-uniform memory access (NUMA) domain, and/or a same compute node.

11. The apparatus of claim 8 , further comprising computer program instructions executed to:
identify, based on a degree of cache misses indicated in the performance activity, a first thread of the plurality of threads and a second thread of the plurality of threads assigned to a same core of the plurality of cores;
wherein modifying the resource allocation comprises assigning one or more of the first thread and the second thread to different cores of the plurality of cores.

12. The apparatus of claim 8 , further comprising computer program instructions executed to:
monitor, after modifying the resource allocation, additional performance activity; and
determine, based on the additional performance activity, whether to undo a modification to the resource allocation.

13. The apparatus of claim 8 , wherein the resource allocation is modified by modifying, for one or more cores of the plurality of cores, one or more thresholds based on the thread each respective core of the one or more cores is executing, wherein the one or more thresholds comprise a package power tracking (PPT) threshold, a thermal design current (TDC) threshold, an electrical design current (EDC) threshold, or a Reliability Limit comprising a threshold amount of time a core can safely spend at a voltage/temperature pair.

14. The apparatus of claim 8 , wherein the data is stored in remote memory.

15. A computer program product for automatic central processing unit (CPU) usage optimization, the CPU including a plurality of cores, the computer program product disposed upon a non-transitory computer readable medium, the computer program product comprising computer program instructions that, when executed, cause a computer to:
modify a resource allocation of the plurality of cores for a plurality of threads based on performance activity of a workload comprising the plurality of threads; and
store data, associated with the workload, indicating the modified resource allocation of the plurality of cores of the CPU, wherein the data indicating the modified resource allocation of the plurality of cores of the CPU is loaded upon a request for execution of the workload and the modified resource allocation is applied to the plurality of cores after the data is loaded.

16. The computer program product of claim 15 , further comprising computer program instruction that, when executed, cause the computer to:
identify, based on the performance activity, a first thread of the plurality of threads and a second thread of the plurality of threads related to the first thread;
wherein the resource allocation is modified by modifying a core assignment to reduce a physical distance between a first core of the plurality of cores assigned the first thread and a second core of the plurality of cores assigned the second thread.

17. The computer program product of claim 16 , wherein the first core and the second core are located within a same compute core complex (CCX), a same core complex die (CCD), a same socket, a same non-uniform memory access (NUMA) domain, and/or a same compute node.

18. The computer program product of claim 15 , further comprising computer program instructions that, when executed, cause the computer to:
identify, based on a degree of cache misses indicated in the performance activi

Assignees

• Advanced Micro Devices Inc

Inventors

• Harwani Anil
• Mehra Amitabh
• Alverson William R
• Ley Grant E
• Ahrens Jerry A
• Mitchell Kenneth

Classifications

• G06F9/5088

  involving task migration · CPC title

• G06F9/544

  Buffers; Shared memory; Pipes · CPC title

• G06F9/54

  Interprogram communication · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F3/065

  Replication mechanisms · CPC title