Read voltage control method, memory storage device and memory control circuit unit

Patent metadata

Field	Value
Publication number	US-12008262-B2
Application number	US-202017080854-A
Country	US
Kind code	B2
Filing date	Oct 27, 2020
Priority date	Oct 7, 2020
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

An exemplary embodiment of the invention provides a read voltage control method for a rewritable non-volatile memory module. The method includes: sending a first read command sequence which instructs a reading of a plurality of first memory cells by using a first voltage level to obtain first data; obtaining first adjustment information of a read voltage according to the first data and a channel parameter of the first memory cells, and the channel parameter reflects a channel status of the first memory cells; and adjusting a voltage level of the read voltage from the first voltage level to a second voltage level according to the first adjustment information.

First claim

What is claimed is:

1. A read voltage control method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells, and the read voltage control method comprises:
sending a first read command sequence which instructs a reading of a plurality of first memory cells in the memory cells by using a first voltage level to obtain first data, wherein the first data is a total number of memory cells turned on by the first voltage level in the first memory cells;
determining a channel parameter according to curve information of a threshold voltage distribution of the first memory cells, wherein the curve information describes at least one of a curve endpoint, a curve type, a curve peak value and a curve slope of the threshold voltage distribution, and the threshold voltage distribution presents a number of memory cells each having a specific threshold voltage among the first memory cells;
obtaining first adjustment information of a read voltage according to the first data and the channel parameter of the first memory cells, wherein the channel parameter reflects a channel status of the first memory cells; and
adjusting a voltage level of the read voltage from the first voltage level to a second voltage level according to the first adjustment information.

2. The read voltage control method of claim 1 , further comprising:
if the channel status of the first memory cells matches a first status, determining the channel status as a first parameter; and
if the channel status of the first memory cells matches a second status, determining the channel status as a second parameter,
wherein the first parameter is different from the second parameter.

3. The read voltage control method of claim 1 , wherein the channel status of the first memory cells comprises a threshold voltage distribution status of the first memory cells.

4. The read voltage control method of claim 1 , further comprising:
adjusting the first adjustment information of the read voltage according to a proportional parameter;
sending a second read command sequence which instructs a reading of the first memory cells by using the second voltage level to obtain second data; and
adjusting the proportional parameter according to the first data and the second data.

5. The read voltage control method of claim 1 , further comprising:
adjusting the first adjustment information of the read voltage according to a proportional parameter;
after adjusting the voltage level of the read voltage to the second voltage level, adjusting the voltage level of the read voltage to a third voltage level; and
adjusting the proportional parameter according to the first adjustment information, the first voltage level and the third voltage level.

6. The read voltage control method of claim 5 , wherein the step of adjusting the proportional parameter according to the first adjustment information, the first voltage level and the third voltage level comprises:
adjusting the proportional parameter according to a difference between the first voltage level and the third voltage level and the first adjustment information.

7. A memory storage device, comprising:
a connection interface unit configured to couple to a host system;
a rewritable non-volatile memory module comprising a plurality of memory cells; and
a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module,
wherein the memory control circuit unit is configured to send a first read command sequence which instructs a reading of a plurality of first memory cells in the memory cells by using a first voltage level to obtain first data, wherein the first data is a total number of memory cells turned on by the first voltage level in the first memory cells,
the memory control circuit unit is further configured to determine a channel parameter according to curve information of a threshold voltage distribution of the first memory cells, wherein the curve information describes at least one of a curve endpoint, a curve type, a curve peak value and a curve slope of the threshold voltage distribution, and the threshold voltage distribution presents a number of memory cells each having a specific threshold voltage among the first memory cells;
the memory control circuit unit is further configured to obtain first adjustment information of a read voltage according to the first data and the channel parameter of the first memory cells, the channel parameter reflects a channel status of the first memory cells, and
the memory control circuit unit is further configured to adjust a voltage level of the read voltage from the first voltage level to a second voltage level according to the first adjustment information.

8. The memory storage device of claim 7 , wherein if the channel status of the first memory cells matches a first status, the memory control circuit unit is further configured to determine the channel status as a first parameter, and
if the channel status of the first memory cells matches a second status, the memory control circuit unit is further configured to determine the channel status as a second parameter,
wherein the first parameter is different from the second parameter.

9. The memory storage device of claim 7 , wherein the channel status of the first memory cells comprises a threshold voltage distribution status of the first memory cells.

10. The memory storage device of claim 7 , wherein the memory control circuit unit is further configured to adjust the first adjustment information of the read voltage according to a proportional parameter,
the memory control circuit unit is further configured to send a second read command sequence which instructs a reading of the first memory cells by using the second voltage level to obtain second data, and
the memory control circuit unit is further configured to adjust the proportional parameter according to the first data and the second data.

11. The memory storage device of claim 7 , wherein the memory control circuit unit is further configured to adjust the first adjustment information of the read voltage according to a proportional parameter,
after adjusting the voltage level of the read voltage to the second voltage level, the memory control circuit unit is further configured to adjust the voltage level of the read voltage to a third voltage level, and
the memory control circuit unit is further configured to adjust the proportional parameter according to the first adjustment information, the first voltage level and the third voltage level.

12. The memory storage device of claim 11 , wherein the operation of adjusting the proportional parameter according to the first adjustment information, the first voltage level and the third voltage level comprises:
adjusting the proportional parameter according to a difference between the first voltage level and the third voltage level and the first adjustment information.

13. A memory control circuit unit for controlling a rewritable non-volatile memory module, the memory control circuit unit comprising:
a host interface, configured to couple to a host system,
a memory interface, configured to couple to a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells; and
a memory management circuit, coupled to the host interface and the memory interface,
wherein the memory management circuit is configured to send a first read command sequence which instructs a reading of a plurality of first memory cells in the memory cells by using a first voltage level to obtain first data, wher

Assignees

• Phison Electronics Corp

Inventors

• Zeng Shih-Jia
• Tsao Chun-Wei
• Wang Chih-Wei
• Lin Wei

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G11C29/021

  in voltage or current generators · CPC title

• G11C11/5671

  using charge trapping in an insulator · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title