NAND page buffer based security operations

Patent metadata

Field	Value
Publication number	US-12007912-B2
Application number	US-202217814395-A
Country	US
Kind code	B2
Filing date	Jul 22, 2022
Priority date	Jun 1, 2022
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

In some implementations, a memory device may resolve a set of latches of a NAND page buffer to a set of initialized values. The memory device may obtain a NAND page buffer initialized data set from the set of initialized values of the set of latches. The memory device may generate a security key using the NAND page buffer initialized data set.

First claim

What is claimed is:

1. A method, comprising:
resolving a set of latches of a NAND page buffer to a set of initialized values, wherein resolving the set of latches to the set of initialized values is based on:
enabling set voltage sources and reset voltage sources of data nodes associated with the set of latches; and
disabling the set voltage sources and the reset voltage sources;

obtaining a NAND page buffer initialized data set from the set of initialized values of the set of latches; and
generating a security key using the NAND page buffer initialized data set.

2. The method of claim 1 , further comprising:
setting a data node, of the data nodes, to a ground voltage;
setting a set of sense nodes of the data node to a control voltage;
initializing a first data cache and a second data cache of the data node to ground voltage based on enabling a set voltage source of the data node and a reset voltage source of the data node; and
enabling the set of sense nodes, wherein the latch of the data node is resolved to an initialized value, of the set of initialized values, based on disabling the set voltage source and the reset voltage source and enabling the set of sense nodes.

3. The method of claim 1 , further comprising:
initializing a set of data caches of a data node, of the data nodes, to an initialized voltage state; and
resolving the latch of the data node to an initialized value, of the set of initialized values, after initializing the set of data caches of the data node.

4. The method of claim 1 , wherein a latch, of the set of latches, is associated with a corresponding group of initialized values of the NAND page buffer initialized data set, and
wherein a quantity of initialized values in the corresponding group of initialized values is based on a width of the NAND page buffer.

5. The method of claim 1 , further comprising:
using the NAND page buffer for a set of memory operations after obtaining the NAND page buffer initialized data set.

6. The method of claim 5 , further comprising:
performing, after obtaining the NAND page buffer initialized data set, at least one of a write operation, a read operation, or an overwrite operation on a set of data nodes, which include the set of latches, of the NAND page buffer.

7. The method of claim 1 , further comprising:
applying an error correction algorithm to the NAND page buffer initialized data set to generate a corrected NAND page buffer initialized data set; and
generating the security key using the corrected NAND page buffer initialized data set.

8. The method of claim 1 , further comprising:
selecting one or more subsets of a set of helper data associated with error correction of the NAND page buffer initialized data set; and
generating, using the one or more subsets of the set of helper data, one or more security keys corresponding to the one or more subsets of the set of helper data.

9. The method of claim 1 , wherein a rate of errors in the NAND page buffer initialized data set is less than 10%.

10. The method of claim 1 , wherein a size of the NAND page buffer initialized data set is based on a quantity of latches in the NAND page buffer.

11. The method of claim 1 , further comprising:
measuring a set of voltages of the set of latches to identify the set of initialized values.

12. The method of claim 1 , wherein the set of latches is a set of static random access memory (SRAM) latches.

13. The method of claim 1 , further comprising:
verifying a security state associated with the NAND page buffer using the security key.

14. The method of claim 1 , further comprising:
generating the security key using a hash-based message authentication code (HMAC) algorithm.

15. The method of claim 1 , further comprising:
resolving the set of latches in connection with a power on of a power cycle of the NAND page buffer; and
maintaining the security key for a duration of the power cycle of the NAND page buffer.

16. The method of claim 1 , further comprising:
resetting the set of latches during a power cycle of the NAND page buffer; and
resolving the set of latches based on resetting the set of latches.

17. The method of claim 16 , further comprising:
resetting the set of latches without power cycling the NAND page buffer.

18. The method of claim 1 , further comprising:
transmitting a set command or a reset command to reset the set of latches; and
transmitting a resolve command to resolve the set of latches after transmitting the set command or the reset command.

19. The method of claim 1 , further comprising:
transmitting a set of commands to the NAND page buffer to cause the NAND page buffer to generate the security key.

20. The method of claim 1 , further comprising:
maintaining the security key while the NAND page buffer is powered on; and
releasing the security key in connection with the NAND page buffer being powered off.

21. A device, comprising:
a NAND page buffer, comprising:
a set of static random access memory (SRAM) latches,
wherein an SRAM latch, of the set of SRAM latches, includes a first enable control associated with a first inverter and a second enable control associated with a second inverter; and

a controller configured to:
control the set of SRAM latches to cause the set of SRAM latches to resolve to a set of initialized values based on enabling set voltage sources and reset voltage sources concurrently for each latch of the set of latches;
obtain the set of initialized values from the set of SRAM latches; and
output the set of initialized values.

22. The device of claim 21 , wherein the controller is configured to control the set of SRAM latches to cause the set of SRAM latches to resolve to the set of initialized values during a power cycle.

23. The device of claim 21 , wherein the controller is configured to:
initialize the first enable control and the second enable control of the SRAM latch to cause the SRAM latch to resolve to an initialized value of the set of initialized values; and
obtain the initialized value from the SRAM latch.

24. The device of claim 21 , wherein a first SRAM latch, of the set of SRAM latches, differs from one or more second SRAM latches, of the set of SRAM latches, with respect to one or more process parameters; and
wherein the set of initialized values are probabilistically based on the one or more process parameters.

25. An apparatus, comprising:
means for initializing a set of data caches of a latch of a data node of a NAND page buffer;
means for resolving the latch of the data node of the NAND page buffer to an initialized value based on:
enabling a set voltage source and a reset voltage source of the data node; and
disabling the set voltage source and the reset voltage source; and

means for obtaining a NAND page buffer initialized data set comprising a set of initialized values for a set of data nodes of the NAND page buffer, wherein the set of initialized values includes the initialized value.

26. The apparatus of claim 25 , further comprises:
means for seeding an algorithm based at least in part on the set of initialized values.

27. The apparatus of claim 26 , wherein the algorithm is at least one of: a random number generation algorithm, a security key generation algorithm, or a hashing algorithm.

28. The apparatus of claim 25 , further comprising:
means for combinin

Assignees

• Micron Technology Inc

Inventors

• Binfet Jeremy
• Dover Lance Walker
• Vali Tommaso
• Di Francesco Walter

Classifications

• G11C16/22 Primary

  Safety or protection circuits preventing unauthorised or accidental access to memory cells · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G06F2212/1052

  Security improvement · CPC title

• G06F21/44

  Program or device authentication · CPC title

• G11C7/24

  Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells · CPC title