Unified retention and wake-up clamp apparatus and method

Patent metadata

Field	Value
Publication number	US-12007826-B2
Application number	US-202017128076-A
Country	US
Kind code	B2
Filing date	Dec 19, 2020
Priority date	Sep 21, 2020
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

Described is a controller that provides in-situ state retention using a closed loop global retention clamp. The controller addresses di/dt and reliability constraints using an adaptive scheme where steps with smaller current are quickly changed whereas steps with larger current are changed slowly. The loop controller of a voltage regulator is modified for controlling not only retention Vmin during a low power state (e.g., C1LP), but also to control fast wake up the low power state (e.g., from C1LP and from C6).

First claim

What is claimed is:

1. An apparatus comprising:
a plurality of power gates coupled to an input power supply rail and an output power supply rail;
a shifter to generate a control word to control the plurality of power gates; and
a controller to instruct the shifter when to shift up a value of the control word, shift down the value of the control word, or maintain the value of the control word, wherein the controller is to shift up or shift in non-monotonic manner to reduce error between a reference beat frequency and a beat frequency of a free-running oscillator.

2. The apparatus of claim 1 , wherein the controller is to operate in retention mode or wakeup mode.

3. The apparatus of claim 2 , wherein, in the retention mode, the controller is to instruct the shifter to shift up the value of the control word when a voltage on the output power supply rail is less than a retention voltage and when the voltage on the output power supply rail has a negative slope or substantially zero slope.

4. The apparatus of claim 2 , wherein, in the retention mode, the controller is to instruct the shifter to shift down the value of the control word when a voltage on the output power supply rail is greater than a retention voltage and when the voltage on the output power supply rail has a positive slope or when the voltage on the output power supply rail has a substantially zero slope.

5. The apparatus of claim 2 , wherein, in the wakeup mode, the controller is to instruct the shifter to shift up the value of the control word if a slope of a voltage on the output power supply rail is less than or equal than a reference slope.

6. The apparatus of claim 2 , wherein, in the wakeup mode, the controller is to instruct the shifter to maintain the value of the control word if a slope of a voltage on the output power supply rail is greater than a reference slope.

7. The apparatus of claim 1 , wherein the free-running oscillator is to generate a first clock, wherein the apparatus comprises a clock synchronizer to synchronize the first clock with a second clock.

8. The apparatus of claim 7 , wherein the controller comprises a counter, wherein the clock synchronizer is to generate a third clock, and wherein the counter is to determine the frequency of the first clock via the third clock.

9. The apparatus of claim 8 , wherein the counter is to receive the second clock.

10. The apparatus of claim 8 , wherein the controller comprises a first comparator to compare an output of the counter with a digital value indicating a past frequency count of the first clock, and wherein the first comparator is to generate an output indicative of a direction in change in frequency of the first clock relative the past frequency count.

11. The apparatus of claim 10 , wherein the controller comprises a second comparator to compare the output of the counter with a reference frequency count, wherein the second comparator is to generate an output indicating an error between the first clock relative to the reference frequency count.

12. The apparatus of claim 11 comprises a logic to generate the control word according to the outputs of the first and second comparators.

13. The apparatus of claim 1 , wherein the plurality of power gates comprises p-type devices.

14. A system comprising:
a memory;
a processor coupled to the memory; and
a wireless interface communicatively coupled to the processor, wherein the processor includes a low dropout regulator comprising:
a plurality of power gates coupled to an input power supply rail and an output power supply rail;
a shifter to generate a control word to control the plurality of power gates; and
a controller to instruct the shifter when to shift up a value of the control word, shift down the value of the control word, or maintain the value of the control word, wherein the controller is to shift up or shift in non-monotonic manner to reduce error between a reference beat frequency and a beat frequency of a free-running oscillator.

15. The system of claim 14 , wherein the controller is to operate in retention mode or wakeup mode.

16. The system of claim 15 , wherein, in the retention mode, the controller is to instruct the shifter to shift up the value of the control word when a voltage on the output power supply rail is less than a retention voltage and when the voltage on the output power supply rail has a negative slope or substantially zero slope.

17. The system of claim 15 , wherein, in the retention mode, the controller is to instruct the shifter to shift down the value of the control word when a voltage on the output power supply rail is greater than a retention voltage and when the voltage on the output power supply rail has a positive slope or when the voltage on the output power supply rail has a substantially zero slope.

18. The system of claim 15 , wherein, in the wakeup mode, the controller is to instruct the shifter to shift up the value of the control word if a slope of a voltage on the output power supply rail is less than or equal than a reference slope.

19. The system of claim 15 , wherein, in the wakeup mode, the controller is to instruct the shifter to maintain the value of the control word if a slope of a voltage on the output power supply rail is greater than a reference slope.

Assignees

• Intel Corp

Inventors

• Augustine Charles
• Meinerzhagen Pascal
• Bang Suyoung
• Afzal Abdullah
• Subramanian Karthik
• Khellah Muhammad
• Raman Arvind

Classifications

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• H03K19/017509 Primary

  Interface arrangements · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title