Controllable temperature coefficient bias circuit

Patent metadata

Field	Value
Publication number	US-12007803-B2
Application number	US-202318359513-A
Country	US
Kind code	B2
Filing date	Jul 26, 2023
Priority date	Oct 25, 2017
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.

First claim

What is claimed is:

1. A controllable temperature coefficient bias circuit including:
(a) a constant current with temperature (CWT) circuit having an output;
(b) a first Current Digital to Analog Converter (IDAC) having a signal input coupled to the output of the CWT circuit and an output;
(c) a Proportional To Ambient Temperature (PTAT) circuit having an output; and
(d) a second IDAC having a signal input coupled to the output of the PTAT circuit and having an output coupled to the output of the first IDAC.

2. The controllable temperature coefficient bias circuit of claim 1 , further including a control processor having a first and second control output and wherein:
(a) the first IDAC includes a control input coupled to the first control output of the control processor and is configured to output a current proportional to signals applied to the first IDAC signal input scaled in response to a first scaling factor received at the control input of the first IDAC; and
(b) the second IDAC includes a control input coupled to the second control output of the control processor and is configured to output a current proportional to signals applied to the second IDAC signal input scaled in response to a second scaling factor received at the control input of the second IDAC.

3. The controllable temperature coefficient bias circuit of claim 2 , wherein a temperature coefficient of the coupled outputs of the first IDAC and the second IDAC may be adjusted by adjusting the relative values of the first and second scaling factors.

4. The controllable temperature coefficient bias circuit of claim 2 , wherein:
(a) the first IDAC includes at least two selectively enabled current mirrors, the current in each enabled current mirror of the first IDAC being summed at the output of the first IDAC; and
(b) the second IDAC includes at least two selectively enabled current mirrors, the current in each enabled current mirror of the second IDAC being summed at the output of the second IDAC.

5. The controllable temperature coefficient bias circuit of claim 4 , wherein a temperature coefficient of the coupled output of the first IDAC and the second IDAC may be adjusted by adjusting the relative values of the first and second scaling factors.

6. The controllable temperature coefficient bias circuit of claim 4 , wherein the at least two current mirrors in the first IDAC are enabled in response to the first scaling factor and the at least two current mirrors in the second IDAC are enabled in response to the second scaling factor.

7. The controllable temperature coefficient bias circuit of claim 1 , wherein the CWT circuit includes:
(a) a transistor having a gate, a drain coupled to a node, and a source, the source configured to be coupled to a voltage supply;
(b) a resistor coupled between the node and configured to be coupled to ground;
(c) a reference voltage source; and
(d) an operational amplifier having a first input coupled to the reference voltage source, a second input coupled to the node, and an output coupled to the gate to the transistor.

8. The controllable temperature coefficient bias circuit of claim 1 , further including a control processor having a first and second control output and wherein:
(a) the first IDAC includes a control input coupled to the first control output of the control processor and is configured to provide an output proportional to a first scaling factor received at the control input of the first IDAC; and
(b) the second IDAC includes a control input coupled to the second control output of the control processor and is configured to provide an output proportional to a second scaling factor received at the control input of the second IDAC.

9. The controllable temperature coefficient bias circuit of claim 8 , wherein a temperature coefficient of the coupled outputs of the first IDAC and the second IDAC may be adjusted by adjusting the relative values of the first and second scaling factors.

10. The controllable temperature coefficient bias circuit of claim 8 , wherein:
(a) the first IDAC includes at least two selectively enabled current mirrors, the current in each enabled current mirror of the first IDAC being summed at the output of the first IDAC; and
(b) the second IDAC includes at least two selectively enabled current mirrors, the current in each enabled current mirror of the second IDAC being summed at the output of the second IDAC.

11. The controllable temperature coefficient bias circuit of claim 10 , wherein a temperature coefficient of the coupled output of the first IDAC and the second IDAC may be adjusted by adjusting the relative values of the first and second scaling factors.

12. The controllable temperature coefficient bias circuit of claim 10 , wherein the at least two current mirrors in the first IDAC are enabled in response to the first scaling factor and the at least two current mirrors in the second IDAC are enabled in response to the second scaling factor.

13. A controllable temperature coefficient bias circuit including:
(a) a constant current with temperature (CWT) circuit having an output;
(b) a first Current Digital to Analog Converter (IDAC) having a signal input coupled to the output of the CWT circuit, a control input, and an output;
(c) a Proportional To Ambient Temperature (PTAT) circuit having an output;
(d) a second IDAC having a signal input coupled to the output of the PTAT circuit, a control input, and an output coupled to the output of the first IDAC; and
(e) a control processor having a first control output coupled to the control input of the first IDAC and configured to output a first scaling factor, and a second control output coupled to the control input of the second IDAC and configured to output a second scaling factor;
wherein the first IDAC is configured to output a current proportional to the first scaling factor and the second IDAC is configured to output a current proportional to the second scaling factor.

14. The controllable temperature coefficient bias circuit of claim 13 , wherein a temperature coefficient of the coupled outputs of the first IDAC and the second IDAC may be adjusted by adjusting the relative values of the first and second scaling factors.

15. The controllable temperature coefficient bias circuit of claim 13 , wherein:
(a) the first IDAC includes at least two selectively enabled current mirrors, the current in each enabled current mirror of the first IDAC being summed at the output of the first IDAC; and
(b) the second IDAC includes at least two selectively enabled current mirrors, the current in each enabled current mirror of the second IDAC being summed at the output of the second IDAC.

16. The controllable temperature coefficient bias circuit of claim 15 , wherein a temperature coefficient of the coupled output of the first IDAC and the second IDAC may be adjusted by adjusting the relative values of the first and second scaling factors.

17. The controllable temperature coefficient bias circuit of claim 15 , wherein the at least two current mirrors in the first IDAC are enabled in response to the first scaling factor and the at least two current mirrors in the second IDAC are enabled in response to the second scaling factor.

18. The controllable temperature coefficient bias circuit of claim 13 , wherein the CWT circuit includes:
(a) a transistor having a gate, a drain coupled to a node, and a source, the source configured to be coupled to a voltage supply;
(b) a resistor coupled between the node and configured to be coupled to ground;
(c) a reference voltage sour

Assignees

• Psemi Corp

Inventors

• Englekirk Robert Mark
• Bargroff Keith
• Murphy Christopher C
• Ranta Tero Tapio

Classifications

• H03M1/742

  using current sources as quantisation value generators · CPC title

• G05F3/242

  with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• G05F3/262 Primary

  using field-effect transistors only · CPC title