Clock data recovery with decision feedback equalization

Patent metadata

Field	Value
Publication number	US-12003354-B2
Application number	US-202318330187-A
Country	US
Kind code	B2
Filing date	Jun 6, 2023
Priority date	Apr 28, 2016
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

Methods and systems are described for generating two comparator outputs by comparing a received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds determined by an estimated amount of inter-symbol interference on a multi-wire bus, selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision, and selecting one of the two comparator outputs as a phase-error decision, the phase error decision selected in response to identification of a predetermined data decision pattern.

First claim

We claim:

1. A method comprising:
receiving a data signal over a series of signaling intervals that forms a signaling eye for a data pattern of a plurality of data patterns, the plurality of data patterns comprising transitioning data patterns;
filtering the data signal to align transitioning signal edge trajectories of each transitioning data pattern with a corresponding one of a plurality of speculative decision feedback equalization (DFE) decision thresholds;
generating, for each speculative DFE decision threshold, a corresponding sample of the data signal using a respective sampler according to a sampling clock, wherein the corresponding sample for a given DFE decision threshold corresponds to (i) a data decision for a first subset of the plurality of data patterns, (ii) an edge sample for a second subset of the plurality of data patterns, and (iii) neither a data decision nor an edge sample for a third subset of the plurality of data patterns;
generating phase-error signals based on each edge sample; and
providing the phase-error signals to a clock recovery circuit to adjust the sampling instant of the sampling clock.

2. The method of claim 1 , further comprising generating the data signal by combining signals received via a plurality of wires of a multi-wire bus, the combining performed according to a sub-channel vector of a plurality of mutually-orthogonal sub-channel vectors.

3. The method of claim 1 , wherein the phase-error signal is an early/late logic decision, and wherein the early/late logic decision is used to update a voltage controlled oscillator in the clock recovery circuit.

4. The method of claim 1 , wherein each data pattern of the plurality of data patterns spans three signaling intervals.

5. The method of claim 1 , wherein the first, second, and third subsets of the plurality of data patterns are mutually exclusive.

6. An apparatus comprising:
a continuous time linear equalizer (CTLE) configured to receive a data signal comprising a plurality of data patterns over a series of signaling intervals and to filter the data signal to generate a filtered data signal having altered signal trajectories;
a voltage comparator configured to generate a sample of the filtered data signal responsive to a sampling clock and according to a decision threshold associated with a decision feedback equalizer coefficient;
a data pattern detection circuit configured to identify a specific data pattern associated with the sample; and
a selection circuit configured to responsively process the sample as (i) a valid data decision, (ii) a phase error sample to provide to a clock recovery circuit for adjusting the sampling clock, or (iii) an unneeded sample which may be ignored.

7. The apparatus of claim 6 , further comprising a multi-input comparator (MIC) configured to generate the data signal by combining signals received via a plurality of wires of a multi-wire bus, the combining performed according to a sub-channel vector of a plurality of mutually-orthogonal sub-channel vectors.

8. The apparatus of claim 7 , wherein the plurality of mutually-orthogonal sub-channel vectors are selected from a Hadamard matrix of size 4, and wherein the signals are received in parallel over four wires of the multi-wire bus.

9. The apparatus of claim 6 , wherein the clock recovery circuit comprises logic configured to receive each edge sample and a corresponding previous data decision, to generate an early/late logic decision, and wherein the early/late logic decision is used to update a voltage controlled oscillator in the clock recovery circuit.

10. The apparatus of claim 6 , wherein the selection circuit is configured to process the sample as the valid data decision based on a historical data decision determined in a previous signaling interval.

11. The apparatus of claim 6 , wherein the selection circuit is configured to process the sample as the phase error sample responsive to the data pattern detection circuit detecting a transitioning data pattern.

12. The apparatus of claim 6 , wherein the selection circuit is configured to process the sample as the unneeded sample which may be ignored responsive to the data pattern detection circuit detecting a non-transitioning pattern and further based on a historical data decision determined in a previous signaling interval.

13. A method comprising:
receiving a data signal comprising a plurality of data patterns over a series of signaling intervals and filtering the data signal to generate a filtered data signal having altered signal trajectories;
generating a sample of the filtered data signal responsive to a sampling clock and according to a decision threshold associated with a decision feedback equalizer coefficient;
identifying a specific data pattern associated with the sample; and
processing the sample as (i) a valid data decision, (ii) a phase error sample to provide to a clock recovery circuit for adjusting the sampling clock, or (iii) an unneeded sample which may be ignored.

14. The method of claim 13 , further comprising receiving signals via a plurality of wires of a multi-wire bus, and generating the data signal by combining the signals according to a sub-channel vector of a plurality of mutually-orthogonal sub-channel vectors.

15. The method of claim 14 , wherein the plurality of mutually-orthogonal sub-channel vectors are selected from a Hadamard matrix of size 4, and wherein the signals are received in parallel over four wires of the multi-wire bus.

16. The method of claim 13 , wherein processing the sample as the phase error sample to provide to a clock recovery circuit for adjusting the sampling clock comprises generating an early/late logic decision based on the phase error sample and a historical data decision.

17. The method of claim 13 , the sample is processed as the valid data decision based on a historical data decision determined in a previous signaling interval.

18. The method of claim 13 , wherein the sample is processed as the phase error sample responsive to the data pattern detection circuit detecting a transitioning data pattern.

19. The method of claim 18 , wherein the transitioning data pattern is a triplet data pattern.

20. The method of claim 13 , wherein the sample is processed as the unneeded sample which may be ignored responsive to detecting a non-transitioning pattern and further based on a historical data decision determined in a previous signaling interval.

Assignees

• Kandou Labs SA

Inventors

• Simpson Richard
• Hormati Ali

Classifications

• H04L25/03949 Primary

  equalizer selection or adaptation based on feedback (multiple signaling inclusive of a precoding command for adapting the transmitter H04L1/0031; feedback for transmit diversity systems H04B7/0619; selection of codebook or precoding matrix for MIMO diversity systems H04B7/0456) · CPC title

• H04L7/0087

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L25/03885

  adaptive · CPC title