Methods and systems for atomic clocks with high accuracy and low Allan deviation

US12003246B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12003246-B2
Application numberUS-202217731795-A
CountryUS
Kind codeB2
Filing dateApr 28, 2022
Priority dateJun 22, 2021
Publication dateJun 4, 2024
Grant dateJun 4, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A system comprises a digital processing circuit, a frequency modulator, an amplitude modulator, and an adder. The digital processing circuit receives an input signal and a correlation signal and generates a frequency tuning parameter and an amplitude modulation parameter. The frequency modulator generates a frequency modulation signal and the correlation signal. The amplitude modulator receives the amplitude modulation parameter and generates an amplitude modulation signal. The adder receives the frequency tuning parameter and the frequency modulation signal and generates a control signal. In some implementations, the system further comprises a DC feedback circuit that receives the input signal and generates a DC compensation signal. In some implementations, the system further comprises a temperature sensor, a temperature compensation circuit, and a second adder.

First claim

Opening claim text (preview).

What is claimed is: 1. A system, comprising: a signal generator circuit having a frequency modulation input and a signal generator output; a transmitter having a signal input, an amplitude modulation input, and a gas cell transmit output, the signal input coupled to the signal generator output; a frequency modulator having a frequency modulation control input and a frequency modulation output, the frequency modulation output coupled to the frequency modulation input; an amplitude modulator having an amplitude modulation control input and an amplitude modulation output, the amplitude modulation output coupled to the amplitude modulation input; and a processing circuit having a processing input, an amplitude modulation control output, and a frequency modulation control output, the amplitude modulation control output coupled to the amplitude modulation control input, and the frequency modulation control output coupled to the frequency modulation control input. 2. The system of claim 1 , wherein the signal generation circuit is configured to provide a first signal at the signal generation output responsive to a frequency modulation signal at the frequency modulation input; and the transmitter is configured to provide a second signal at the gas cell transmit output responsive to the first signal at the signal input and an amplitude modulation signal at the amplitude modulation input. 3. The system of claim 1 , wherein the processing circuit has a sensor input and configured to: receive a temperature sensor signal at the sensor input; and provide a frequency modulation control signal at the frequency modulation control output responsive to the temperature sensor signal. 4. The system of claim 1 , further comprising a gas cell having a first terminal and a second terminal, the first terminal coupled to the gas cell transmit output, and the second terminal coupled to the processing input, wherein the gas cell is configured to receive a first signal at the first terminal and provide a second signal at the second terminal by removing a particular frequency component of the first signal. 5. The system of claim 1 , wherein: the system further comprises a feedback circuit having a gas cell receive input and a feedback output, the feedback output coupled to the processing input, and the feedback circuit configured to provide a DC bias correction signal at the feedback output responsive to a first signal at the gas cell receive input; and the processing circuit is configured to provide the at least one of a frequency modulation control signal at the frequency modulation control output or an amplitude modulation control signal at the amplitude modulation control output responsive to a difference between the first signal and the DC bias correction signal. 6. The system of claim 5 , wherein the processing circuit includes an anti-aliasing filter configured to filter the difference, and the processing circuit is configured to provide the at least one of the frequency modulation control signal or the amplitude modulation control signal responsive to the filtered difference. 7. The system of claim 2 , wherein the signal generation circuit includes: a fractional-N synthesizer having a reference signal input, a synthesizer control input, and a synthesizer output, the synthesizer control input coupled to the frequency modulation input, and the fractional-N synthesizer configured to provide a third signal at the synthesizer output by multiplying a frequency of a reference signal at the reference signal input based on a state of the synthesizer control input; and a frequency multiplier having a multiplier input and a multiplier output, the multiplier input coupled to the synthesizer output, and the multiplier output coupled to the signal generation output. 8. The system of claim 7 , wherein: the processing circuit has a third control output and configured to provide a frequency modulation cancellation signal at the third control output; and the system further comprises a fractional-N frequency divider having a divider input, a divider control input, and a divider output, the divider input coupled to the synthesizer output, and the divider control input coupled to the third control output. 9. The system of claim 7 , wherein: the fractional-N synthesizer is a first fractional-N synthesizer; the synthesizer output is a first synthesizer output; the frequency modulation signal includes a frequency tuning component and a frequency modulated signal component; the processing circuit has a third control output and configured to provide a third control signal at the third control output based on the frequency tuning component; and the system further comprises a second fractional-N synthesizer having the reference signal input, a second synthesizer control input, and a second synthesizer output, the frequency tuning input coupled to the third control output. 10. The system of claim 7 , wherein: the fractional-N synthesizer is a first fractional-N synthesizer; the synthesizer output is a first synthesizer output; the reference signal input is a first reference signal input; the frequency modulation signal includes a frequency tuning component and a frequency modulated signal component; the processing circuit has a third control output and configured to provide a third control signal at the third control output based on the frequency tuning component; and the system further comprises a second fractional-N synthesizer having a second reference signal input, a second synthesizer control input, and a second synthesizer output, the second synthesizer control input coupled to the third control output, and the second synthesizer output coupled to the first reference signal input. 11. The system of claim 7 , wherein: the frequency modulation signal includes a frequency tuning component and a frequency modulated signal component; the processing circuit has a third control output and configured to provide a third control signal at the third control output based on the frequency tuning component; and the signal generation circuit includes a reference signal generator having a frequency tuning input and a reference signal output, the frequency tuning input coupled to the third control output, and the reference signal output coupled to the reference signal input. 12. The system of claim 11 , wherein the processing circuit has a sensor input and configured to: receive a temperature sensor signal at the sensor input; and provide the third control signal at the third control output responsive to the temperature sensor signal. 13. The system of claim 1 , wherein the processing circuit is configured to provide a frequency modulation control signal at the frequency modulation control output, and the frequency modulation control signal includes a frequency tuning component and a frequency modulated signal component; and wherein the processing circuit is configured to: perform a first correlation between a first signal at the processing input and a second signal including the frequency modulated signal component to generate a first correlation output signal, the second signal having a first frequency within a first interval and a second frequency within a second interval; generate the frequency tuning component based on the first correlation output signal; perform a second correlation between the first correlation output signal and a third signal to generate a second correlation output signal, the third signal alternating between a first state within the first interval and a second state within the second interval; and generate an amplitude modulation control sig

Assignees

Inventors

Classifications

  • H03L7/26Primary

    using energy levels of molecules, atoms, or subatomic particles as a frequency reference · CPC title

  • using atomic clocks · CPC title

  • Generating or distributing clock signals or signals derived directly therefrom · CPC title

  • Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature {(to maintain energy constant H03K3/015)} · CPC title

  • Changing the frequency (modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68) · CPC title

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What does patent US12003246B2 cover?
A system comprises a digital processing circuit, a frequency modulator, an amplitude modulator, and an adder. The digital processing circuit receives an input signal and a correlation signal and generates a frequency tuning parameter and an amplitude modulation parameter. The frequency modulator generates a frequency modulation signal and the correlation signal. The amplitude modulator receives…
Who is the assignee on this patent?
Texas Instruments Inc
What technology area does this patent fall under?
Primary CPC classification H03L7/26. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 04 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).