Switching device for driving an actuator

Patent metadata

Field	Value
Publication number	US-12002888-B2
Application number	US-202117196354-A
Country	US
Kind code	B2
Filing date	Mar 9, 2021
Priority date	Mar 9, 2021
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

A device includes a first transistor having a first source, a first gate, a first drain, and one or more electrodes. The first transistor serves as an inverter. The device also includes a second transistor having a second source, a second gate, and a second drain. The first and second sources are connected together. The first and second drains are connected together. The second transistor serves as an output, a driver, or both. The one or more electrodes, the second gate, or a combination thereof serve as tapped drains that are configured to sample a stepped voltage of the second transistor.

First claim

What is claimed is:

1. A device, comprising:
an optical switch configured to convert light into electrical current;
a first transistor connected to the optical switch, wherein the first transistor comprises a first source, a first gate, a first drain, and one or more electrodes, wherein the first transistor serves as an inverter;
a second transistor comprising a second source, a second gate, and a second drain, wherein the first and second sources are connected together, wherein the first and second drains are connected together, wherein the second transistor serves as an output, a driver, or both, and wherein the one or more electrodes, the second gate, or a combination thereof serve as tapped drains that are configured to sample a stepped voltage of the second transistor;
an interlevel dielectric layer; and
a source-drain (S/D) metal layer positioned at least partially within the interlevel dielectric layer, wherein the optical switch is positioned on first and second portions of the S/D metal layer, and wherein the first and second portions are separated from one another by a portion of the interlevel dielectric layer.

2. The device of claim 1 , wherein the one or more electrodes comprise a plurality of electrodes that are spaced apart from one another between the first gate and the first drain, and wherein the electrodes are positioned within a drift region of an ungated channel of the first transistor.

3. The device of claim 1 , wherein the first transistor is narrower than the second transistor.

4. The device of claim 1 , wherein semiconductor channels of the first and second sources are separated such that the first and second sources are not shared.

5. The device of claim 1 , wherein semiconductor channels of the first and second drains are separated such that the first and second drains are not shared.

6. The device of claim 1 , wherein the first transistor comprises a first electrode and a second electrode that are spaced apart from one another, wherein the second transistor comprises a first field plate and a second field plate that are spaced apart from one another, wherein the first electrode is connected to the first field plate, and wherein the second electrode is connected to the second field plate.

7. The device of claim 6 , wherein the gate of the second transistor is connected to the first electrode.

8. The device of claim 6 , wherein the first and second field plates are positioned at least partially between the gate of the second transistor and the drain of the second transistor.

9. The device of claim 6 , wherein the first and second electrodes are distributed across a high-voltage drift region of an ungated channel of the first transistor.

10. The device of claim 9 , wherein the first and second electrodes are positioned between the gate and the drain of the first transistor.

11. A switching device for driving an actuator, the switching device comprising:
an optical switch configured to convert light into electrical current;
a first transistor connected to the optical switch, wherein the first transistor is configured to serve as an inverter, and wherein the first transistor comprises:
a first source;
a first gate;
a first drain; and
a plurality of electrodes that are spaced apart from one another, wherein the electrodes are positioned at least partially between the first gate and the first drain;

a second transistor configured to serve as an output, a driver, or both, wherein the second transistor comprises:
a second source, wherein the first and second sources are connected together;
a second gate;
a second drain, wherein the first and second drains are connected together; and
a plurality of field plates that are spaced apart from one another, wherein the field plates are positioned at least partially between the second source and the second drain, wherein each field plate is connected to one of the electrodes, and wherein the electrodes, the second gate, or a combination thereof serve as tapped drains that are configured to sample stepped voltages of the second transistor and to provide a voltage for the field plates of the second transistor;

a gate dielectric layer;
an interlevel dielectric layer positioned on the gate dielectric layer;
a passivation layer positioned on the interlevel dielectric layer, wherein the optical switch is positioned at least partially within the interlevel dielectric layer, the passivation layer, or both; and
a source-drain (S/D) metal layer positioned at least partially within the interlevel dielectric layer, wherein the optical switch is positioned on the S/D metal layer, wherein the optical switch is positioned on first and second portions of the S/D metal layer, and wherein the first and second portions are separated from one another by a portion of the interlevel dielectric layer.

12. The switching device of claim 11 , wherein the gate of the second gate is connected to one of the electrodes.

13. The switching device of claim 11 , wherein the electrodes are distributed across a high-voltage drift region of an ungated channel of the first transistor.

14. The switching device of claim 11 , wherein the field plates are configured to distribute high-voltage substantially uniformly across an ungated channel of the second transistor.

15. The switching device of claim 11 , wherein an ungated channel of the first transistor is positioned at least partially between the gate of the first transistor and the drain of the first transistor, and wherein an ungated channel of the second transistor is positioned at least partially between the source of the second transistor and the drain of the second transistor.

16. A high-voltage switching device for driving a microelectromechanical systems (MEMS) actuator, the switching device comprising:
an optical switch configured to convert light into electrical current;
a first transistor connected to the optical switch, wherein the first transistor is configured to serve as an inverter, wherein the first transistor comprises:
a first source;
a first gate;
a first drain; and
a plurality of electrodes that are spaced apart from one another across a high-voltage drift region of an ungated channel of the first transistor, wherein the electrodes and the ungated channel of the first transistor are positioned at least partially between the first gate and the first drain;

a second transistor configured to serve as an output, a driver, or both, wherein the second transistor comprises:
a second source, wherein the first and second sources are connected together;
a second gate, wherein the gate of the second gate is connected to one of the electrodes;
a second drain, wherein the first and second drains are connected together; and
a plurality of field plates that are spaced apart from one another across an ungated channel of the second transistor, wherein the field plates are configured to distribute high-voltage substantially uniformly across the ungated channel of the second transistor, wherein the field plates and the ungated channel of the second transistor are positioned at least partially between the second source and the second drain, wherein each field plate is connected to one of the electrodes, wherein the electrodes, the second gate, or a combination thereof serve as tapped drains that are distributed between the first gate and the first drain, and wherein the tapped drains are configured to sample stepped voltages of the second transistor and to provide a voltage for the field plates of the second transistor;

a gate dielectric layer;
an interlevel dielectric layer positioned

Assignees

• Xerox Corp

Inventors

• Lu Jengping

Classifications

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

• H10D86/40 Primary

  characterised by multiple TFTs · CPC title

• H10D86/471

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D64/112

  comprising multiple field plate segments · CPC title