Array substrate and method for manufacturing the same, and display device

Patent metadata

Field	Value
Publication number	US-12002887-B2
Application number	US-202318343279-A
Country	US
Kind code	B2
Filing date	Jun 28, 2023
Priority date	Dec 12, 2017
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

The embodiments of the present disclosure provide an array substrate and a method for manufacturing the same, and a display device. The array substrate includes a substrate, wherein the substrate has a display region and a peripheral region surrounding the display region, the display region has a plurality of pixels arranged in an array, and each of the plurality of pixels includes a light transmission region and a light shielding region, and a light shielding block covering at least a part of the light transmission region of at least one pixel close to the peripheral region of the plurality of pixels.

First claim

What is claimed is:

1. A display substrate comprising:
a substrate including a display region and a peripheral region surrounding the display region, the display region having a plurality of pixels arranged in an array, and each of the plurality of pixels comprising a light transmission region and a light shielding region; and
a light shielding block for defining the light transmission region and the light shielding region,
an edge pixel located at boundary of the display region, wherein the edge pixel comprises at least three sub-pixels of different color, in one of the at least three sub-pixels, the light shielding block comprising a first portion, a second portion, and a third portion between the first portion and the second portion, the first, second, and third portions separated from each other.

2. The display substrate according to claim 1 , wherein the first portion, the third portion, and the second portion are arranged orderly along a longitude direction of the one of the at least three sub-pixels.

3. The display substrate according to claim 1 , wherein the light shielding block within each of the at least three sub-pixels has a same area.

4. The display substrate according to claim 1 , wherein the first portion and the second portion are substantially symmetric with respect to the third portion.

5. The display substrate according to claim 1 , wherein a ratio of an area of the light shielding block of the one of the at least three sub-pixels is negative correlated with a distance to the peripheral region.

6. The display substrate according to claim 1 , wherein a ratio of an area of the light shielding block to an area of the one of the at least three sub-pixels close to the peripheral region is set as one of N values constituting an arithmetic progression, wherein 3≤N≤101, and wherein the arithmetic progression has a first item of 0 and a last item of 100%.

7. The display substrate according to claim 6 , wherein an absolute value of a difference between the one of the N values and a desired set value depending on a shape of an edge of the display region is smaller than an absolute value of a difference between any other one of the N values and the desired set value.

8. The display substrate according to claim 6 , wherein N is equal to 3, and wherein the arithmetic progressions are 0, 50%, 100%, respectively.

9. The display substrate according to claim 6 , wherein N is equal to 4, and wherein the arithmetic progressions are 0, 33.3%, 66.6%, 100%, respectively.

10. The display substrate according to claim 6 , wherein N is equal to 9, and wherein the arithmetic progression are 0, 12.5%, 25%, 37.5%, 50%, 62.5%, 75%, 87.5%, 100%, respectively.

11. The display substrate according to claim 1 , further comprising:
a thin film transistor located on the substrate and in the light shielding region, the thin film transistor comprising an active layer on the substrate; and
a light shielding layer located between the active layer and the substrate,
wherein the light shielding block is disposed on a same layer as the light shielding layer.

12. The display substrate according to claim 1 , further comprising:
a thin film transistor located on the substrate and in the light shielding region, the thin film transistor comprising an active layer, a gate electrode, and a gate dielectric layer therebetween, wherein the light shielding block is disposed on a same layer as the gate electrode.

13. The display substrate according to claim 1 , further comprising:
a thin film transistor located on the substrate and in the light shielding region, the thin film transistor comprising an active layer, a gate electrode, a gate dielectric layer therebetween, and a source/drain electrode disposed on the active layer, wherein the light shielding block is disposed on a same layer as the source/drain electrode.

14. The display substrate according to claim 1 , wherein the display region has a non-rectangular shape.

15. The display substrate according to claim 1 , wherein the light shielding block is absent in a region surrounded by boundary lines of sub-pixels of the plurality of pixels located in the display region.

16. A display device comprising the display substrate according to claim 1 .

Assignees

• Ordos Yuansheng Optoelectronics Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Chen Yanqing
• Xie Jianyun
• Li Wei
• Li Cheng
• Guo Pan
• Li Yanfeng
• Qin Weida
• Wang Ning

Classifications

• H10W42/20

  protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons · CPC title

• H10D86/021

  of multiple TFTs · CPC title

• H10D30/6723 Primary

  having light shields · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title