Display substrate, method for manufacturing same, and display device

Patent metadata

Field	Value
Publication number	US-12002817-B2
Application number	US-202017604971-A
Country	US
Kind code	B2
Filing date	Dec 14, 2020
Priority date	Dec 14, 2020
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

Provided is a display substrate. The display substrate includes including a base substrate having a first display region and a second display region; in the pixel circuit included in the pixels in the second display region, the conductive line connected to the metal layer is a transparent conductive line, and the transparent conductive line is disposed between the two existing insulating layers.

First claim

What is claimed is:

1. A display substrate, comprising:
a base substrate having a first display region and a second display region, wherein the first display region is at least partially disposed around the second display region; and
a plurality of pixels, each comprising a pixel circuit and a target electrode connected to each other, wherein the pixel circuit is disposed in one of the first display region and the second display region, and the target electrode is disposed in the second display region; and the pixel circuit comprises a first metal layer, a first insulating layer, at least one transparent conductive line, a second insulating layer, and a second metal layer which are disposed on a side of the base substrate and sequentially stacked, each of the at least one transparent conductive line being connected to one metal layer in the pixel circuit.

2. The display substrate according to claim 1 , wherein the first metal layer is a first source-drain metal layer, the second metal layer is a second source-drain metal layer, the first insulating layer is a passivation layer, and the second insulating layer is a first planarization layer.

3. The display substrate according to claim 1 , wherein a material of each of the at least one transparent conductive line is indium tin oxide.

4. The display substrate according to claim 1 , wherein the target electrode is an anode.

5. The display substrate according to claim 1 , wherein the pixel circuit is disposed in the second display region, and an orthographic projection of the pixel circuit on the base substrate is at least partially overlapped with an orthographic projection of the target electrode on the base substrate.

6. The display substrate according to claim 1 , wherein the pixel circuit is disposed in the first display region, and the pixel circuit is connected to the target electrode through the transparent conductive line.

7. The display substrate according to claim 1 , wherein the at least one transparent conductive line comprises a first transparent conductive line;
wherein the first transparent conductive line is connected to the first metal layer and is configured to transmit a power signal, and the first transparent conductive lines in two adjacent pixel circuits disposed in the same column are integrally formed.

8. The display substrate according to claim 1 , wherein the at least one transparent conductive line comprises a second transparent conductive line;
wherein the second transparent conductive line is connected to the second metal layer and is configured to transmit a data signal, and the second transparent conductive lines in two adjacent pixel circuits disposed in the same column are integrally formed.

9. The display substrate according to claim 1 , wherein the pixel circuit further comprises a third insulating layer disposed on a side of the second metal layer distal from the base substrate, and a transistor pattern layer, a third metal layer, a fourth metal layer, and a fourth insulating layer which are disposed between the base substrate and the first metal layer and sequentially stacked in a direction going away from the base substrate.

10. The display substrate according to claim 9 , wherein the third insulating layer is a second planarization layer, the third metal layer is a first gate metal layer, the fourth metal layer is a second gate metal layer, and the fourth insulating layer is an interlayer dielectric layer.

11. The display substrate according to claim 10 , wherein the third metal layer comprises a first portion, a second portion, and a third portion; the at least one transparent conductive line comprises a third transparent conductive line, a fourth transparent conductive line, and a fifth transparent conductive line; wherein
the third transparent conductive line is connected to the first portion and is configured to transmit a light emission control signal, and the third transparent conductive lines in two adjacent pixel circuits disposed in the same row are integrally formed;
the fourth transparent conductive line is connected to the second portion and is configured to transmit a gate driving signal, and the fourth transparent conductive lines in two adjacent pixel circuits disposed in the same row are integrally formed; and
the fifth transparent conductive line is connected to the third portion and is configured to transmit a reset signal, and the fifth transparent conductive lines in two adjacent pixel circuits disposed in the same row are integrally formed.

12. The display substrate according to claim 11 , wherein the at least one transparent conductive line comprises a sixth transparent conductive line;
wherein the sixth transparent conductive line is connected to the fourth metal layer and is configured to transmit an initial signal, and the sixth transparent conductive lines in two adjacent pixel circuits disposed in the same row are integrally formed.

13. The display substrate according to claim 1 , wherein the second display region is a light-transmitting display region.

14. The display substrate according to claim 1 , wherein a resolution of the first display region is greater than or equal to a resolution of the second display region.

15. The display substrate according to claim 1 , wherein each of the at least one transparent conductive line is connected to one metal layer in the pixel circuit through a via hole.

16. The display substrate according to claim 11 , wherein the first metal layer is a first source-drain metal layer, the second metal layer is a second source-drain metal layer, the first insulating layer is a passivation layer, and the second insulating layer is a first planarization layer; a material of each of the at least one transparent conductive line is indium tin oxide; and the target electrode is an anode;
in the case that the pixel circuit is disposed in the second display region, an orthographic projection of the pixel circuit on the base substrate is at least partially overlapped with an orthographic projection of the target electrode on the base substrate; and in the case that the pixel circuit is disposed in the first display region, the pixel circuit is connected to the target electrode through the transparent conductive line; and
the at least one transparent conductive line comprises a first transparent conductive line, a second transparent conductive line, and a sixth transparent conductive line; wherein the first transparent conductive line is connected to the first metal layer and is configured to transmit a power signal, and the first transparent conductive lines in two adjacent pixel circuits disposed in the same column are integrally formed; the second transparent conductive line is connected to the second metal layer and is configured to transmit a data signal, and the second transparent conductive lines in two adjacent pixel circuits disposed in the same column are integrally formed; the sixth transparent conductive line is connected to the fourth metal layer and is configured to transmit an initial signal, and the sixth transparent conductive lines in two adjacent pixel circuits disposed in the same row are integrally formed; the second display region is a light-transmitting display region; a resolution of the first display region is greater than or equal to a resolution of the second display region; and each of the at least one transparent conductive line is connected to one metal layer in the pixel circuit through a via hole.

17. A method for manufacturing a display substrate, comprising:
providing a base substrate, wherein the base substrate has a

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd
• Chengou Boe Optoelectronics Tech Co Ltd

Inventors

• Shi Ling
• Chen Yipeng
• Liu Ke
• Fang Fei
• Zhang Zhenhua
• Tian Xuewei

Classifications

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/021

  of multiple TFTs · CPC title

• H01L27/124 Primary

  Electricity · mapped topic