Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-12002517-B2
Application number	US-202117534210-A
Country	US
Kind code	B2
Filing date	Nov 23, 2021
Priority date	Jul 1, 2021
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

A semiconductor memory device includes a memory cell array, a page buffer, and control logic. The memory cell array includes a plurality of memory cells for storing data. The page buffer is coupled to at least one memory cell among the plurality of memory cells through a bit line and is configured to store data in the at least one memory cell. The control logic is configured to control an operation of the page buffer. The page buffer includes a first transistor coupled between the bit line and a first node, a second transistor coupled between the bit line and an external power voltage terminal, and an internal operation circuit coupled to the first node.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells for storing data;
a page buffer coupled to at least one memory cell among the plurality of memory cells through a bit line and configured to store data in the at least one memory cell; and
control logic configured to control an operation of the page buffer,
wherein the page buffer comprises:
a first transistor coupled between the bit line and a first node;
a second transistor coupled between the bit line and an external power voltage terminal; and
an internal operation circuit coupled to the first node,

wherein the control logic is configured to:
control, when a program inhibit bias is transmitted to the bit line, the page buffer to transmit the program inhibit bias from the internal operation circuit to the bit line by turning on the first transistor and disconnect between the external power voltage terminal and the bit line by turning off the second transistor; and
apply, to suppress occurrence of a leakage current from a side of the bit line to a side of the second transistor, a first voltage greater than 0V to the external power voltage terminal while the program inhibit bias is transmitted to the bit line during a program operation.

2. The semiconductor memory device of claim 1 , wherein:
the page buffer further comprises a third transistor coupled between the first node and ground; and
the control logic is configured to control the page buffer to disconnect between the first node and the ground by turning off the third transistor while the program inhibit bias is transmitted to the bit line.

3. The semiconductor memory device of claim 1 , wherein the internal operation circuit is configured to:
receive a power voltage from an internal power voltage terminal; and
output a second voltage supplied by the internal power voltage terminal to the first node as the program inhibit bias.

4. The semiconductor memory device of claim 1 , wherein the internal operation circuit is configured to:
receive a power voltage from an internal power voltage terminal; and
output a third voltage generated based on a second voltage supplied from the internal power voltage terminal to the first node as the program inhibit bias.

5. The semiconductor memory device of claim 1 , wherein the first voltage is between 0.5 volt and 1 volt.

6. The semiconductor memory device of claim 1 , wherein the first transistor is a high-voltage protection transistor.

7. The semiconductor memory device of claim 1 , wherein the internal operation circuit comprises:
a fourth transistor coupled between the first node and a second node;
a fifth transistor coupled between an internal power voltage terminal and a third node;
a sixth transistor coupled between the second node and the third node;
a seventh transistor coupled between the third node and a fourth node; and
an eighth transistor coupled between the second node and the fourth node.

8. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells for storing data;
a page buffer coupled to at least one memory cell among the plurality of memory cells through a bit line and configured to erase data stored in the at least one memory cell; and
control logic configured to control an operation of the page buffer,
wherein the page buffer comprises:
a first transistor coupled between the bit line and a first node;
a second transistor coupled between the first node and a ground;
a third transistor coupled between the bit line and an external power voltage terminal; and
an internal operation circuit coupled to the first node,

wherein the control logic is configured to:
apply, when an erase bias is applied to the bit line, an erase voltage to the external power voltage terminal;
control the page buffer to connect the external power voltage terminal and the bit line by turning on the third transistor; and
apply, to increase a breakdown voltage in a junction overlap region of the first transistor, a first voltage greater than 0V and less than a turn-on voltage to a gate of the first transistor while the erase voltage is applied to the bit line through the external power voltage terminal during an erase operation.

9. The semiconductor memory device of claim 8 , wherein the control logic is configured to control the page buffer to apply the turn-on voltage greater than the erase voltage to a gate of the third transistor.

10. The semiconductor memory device of claim 8 , wherein the first voltage is between 1 volt and 2 volts.

11. The semiconductor memory device of claim 8 , wherein the first transistor is a high-voltage protection transistor.

12. The semiconductor memory device of claim 8 , wherein the control logic is configured to, while the erase bias is transmitted to the bit line, control the page buffer to disconnect between the first node and the ground by turning off the second transistor.

13. The semiconductor memory device of claim 8 , wherein the internal operation circuit comprises:
a fourth transistor coupled between the first node and a second node;
a fifth transistor coupled between an internal power voltage terminal and a third node;
a sixth transistor coupled between the second node and the third node;
a seventh transistor coupled between the third node and a fourth node; and
an eighth transistor coupled between the second node and the fourth node.

14. The semiconductor memory device of claim 13 , wherein the control logic is configured to control the page buffer to disconnect between the first node and the second node by turning off the fourth transistor while the erase bias is transmitted to the bit line.

Assignees

• Sk Hynix Inc

Inventors

• Lee Hee Youl

Classifications

• G11C16/24 Primary

  Bit-line control circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/14 Primary

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/3427 Primary

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title