Apparatus and method for efficient graphics processing including ray tracing

Patent metadata

Field	Value
Publication number	US-12002145-B2
Application number	US-202017133573-A
Country	US
Kind code	B2
Filing date	Dec 23, 2020
Priority date	Aug 17, 2020
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

Apparatus and method for efficient graphics processing including ray tracing. For example, one embodiment of a graphics processor comprises: execution hardware logic to execute graphics commands and render images; an interface to couple functional units of the execution hardware logic to a tiled resource; and a tiled resource manager to manage access by the functional units to the tiled resource, a functional unit of the execution hardware logic to generate a request with a hash identifier (ID) to request access to a portion of the tiled resource, wherein the tiled resource manager is to determine whether a portion of the tiled resource identified by the hash ID exists, and if not, to allocate a new portion of the tiled resource and associate the new portion with the hash ID.

First claim

What is claimed is:

1. A graphics processor comprising:
execution hardware logic to execute graphics commands and render images;
an interface to couple functional units of the execution hardware logic to a tiled resource; and
a tiled resource manager to manage access by the functional units to the tiled resource, a functional unit of the execution hardware logic to generate a request with a hash identifier (ID) to request access to a portion of the tiled resource,
wherein the tiled resource manager is to determine whether a portion of the tiled resource identified by the hash ID exists; if not, to allocate a new portion of the tiled resource and associate the new portion with the hash ID, and upon no new portion of the tiled resources being found, to evict an existing portion of the tiled resource and to reallocate the existing portion as the new portion associated with the hash ID.

2. The graphics processor of claim 1 wherein the tiled resource manager is to implement a least recently used (LRU) eviction policy to evict the existing portion of the tiled resource used least recently.

3. The graphics processor of claim 1 wherein if a portion of the tiled resource identified by the hash ID exists, then the tiled resource manager is to provide access to the portion of the tiled resource.

4. The graphics processor of claim 3 wherein the portion of the tiled resource comprises a fixed-size resource tile.

5. The graphics processor of claim 4 wherein the tiled resource comprises a memory buffer subdivided into tiles.

6. The graphics processor of claim 5 further comprising:
ray traversal hardware logic coupled to the memory buffer, the ray traversal hardware logic to trace a ray through an acceleration data structure, the ray having an associated instance identifier (ID),
wherein the hash ID is generated based in the instance ID.

7. The graphics processor of claim 6 wherein the hash ID is generated based on a combination of the instance ID and a frame counter.

8. The graphics processor of claim 1 wherein if a new portion of the tiled resource is allocated, then the execution hardware logic is to execute a user compute shader, the user compute shader to store triangles in the portion of the tiled resource.

9. The graphics processor of claim 3 wherein if the portion of the tiled resource is not new, then the execution hardware logic is to execute an intersection shader to perform ray/triangle intersections, the intersection shader to be provided a pointer to the portion of the tiled resource.

10. A method comprising:
executing graphics commands and rendering images by execution hardware logic, the execution hardware logic coupled to a tiled resource;
generating a request with a hash identifier (ID) to request access to a portion of the tiled resource, the request generated by a functional unit of the execution hardware logic;
determining whether a portion of the tiled resource identified by the hash ID exists;
if a portion of the tiled resource identified by the hash ID does not exist and a new portion of the tiled resource is found, allocating the new portion of the tiled resource and associating the new portion with the hash ID; and
if a portion of the tiled resource identified by the hash ID does not exist and the new portion of the tiled resource is not found, evicting an existing portion of the tiled resource, and reallocating the existing portion as the new portion associated with the hash ID.

11. The method of claim 10 wherein evicting comprises implementing a least recently used (LRU) eviction policy to remove an existing portion of the tiled resource used least recently.

12. The method of claim 10 wherein if a portion of the tiled resource identified by the hash ID exists, then providing access to the portion of the tiled resource.

13. The method of claim 12 wherein the portion of the tiled resource comprises a fixed-size resource tile.

14. The method of claim 13 wherein the tiled resource comprises a memory buffer subdivided into tiles.

15. The method of claim 14 further comprising:
tracing a ray through an acceleration data structure by ray traversal hardware logic coupled to the memory buffer, the ray having an instance identifier (ID) associated therewith, wherein the hash ID is generated based in the instance ID.

16. The method of claim 15 wherein the hash ID is generated based on a combination of the instance ID and a frame counter.

17. The method of claim 10 wherein if a new portion of the tiled resource is allocated, then executing a user compute shader, the user compute shader to store triangles in the portion of the tiled resource.

18. The method of claim 12 wherein if the portion of the tiled resource is not new, then executing an intersection shader to perform ray/triangle intersections, the intersection shader to be provided a pointer to the portion of the tiled resource.

19. A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform:
executing graphics commands and rendering images by execution hardware logic, the execution hardware logic coupled to a tiled resource;
generating a request with a hash identifier (ID) to request access to a portion of the tiled resource, the request generated by a functional unit of the execution hardware logic;
determining whether a portion of the tiled resource identified by the hash ID exists;
if a portion of the tiled resource identified by the hash ID does not exist and a new portion of the tiled resource is found, allocating the new portion of the tiled resource and associating the new portion with the hash ID; and
if a portion of the tiled resource identified by the hash ID does not exist and the new portion of the tiled resource is not found, evicting an existing portion of the tiled resource, and reallocating the existing portion as the new portion associated with the hash ID.

20. The non-transitory machine-readable medium of claim 19 wherein evicting comprises implementing a least recently used (LRU) eviction policy to remove an existing portion of the tiled resource used least recently.

21. The non-transitory machine-readable medium of claim 19 wherein if a portion of the tiled resource identified by the hash ID exists, then the machine is to provide access to the portion of the tiled resource.

22. The non-transitory machine-readable medium of claim 21 wherein the portion of the tiled resource comprises a fixed-size resource tile.

Assignees

• Intel Corpoation
• Intel Corp

Inventors

• Woop Sven
• Doyle Michael J
• Kothandaraman Sreenivas
• Vaidyanathan Karthik
• Appu Abhishek R
• Benthin Carsten
• Surti Prasoonkumar
• Gruen Holger
• Junkins Stephen
• Lake Adam
• Alfieri Bret G
• Liktor Gabor
• Barczak Joshua
• Lee Won-Jong

Classifications

• G06T15/06 Primary

  Ray-tracing · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T1/60

  Memory management · CPC title

• G06T15/005

  General purpose rendering architectures · CPC title

• G06T2210/21

  Collision detection, intersection · CPC title