PIM computing system and memory controller thereof

Patent metadata

Field	Value
Publication number	US-12001682-B2
Application number	US-202218068995-A
Country	US
Kind code	B2
Filing date	Dec 20, 2022
Priority date	Jun 24, 2022
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

A Processing-in-Memory (PIM) computing system and a memory controller provide improved memory traffic efficiency and improved PIM operation efficiency by increasing a burst length of a PIM operation relative to a general memory request. In embodiments, the increased burst length allows the PIM operation to be performed in units of pages, wherein a page is management unit of a memory used in the PIM operation.

First claim

What is claimed is:

1. A Processing-in-Memory (PIM) computing system comprising:
a Random Access Memory (RAM) configured to perform a PIM operation of reading data of a second read granularity corresponding to a second burst length in response to receiving a PIM request when the PIM request includes a read command; and
a memory controller configured to:
identify a first memory request as the PIM request by comparing an address of the first memory request with pre-registered PIM address information,
schedule a memory request by applying the second burst length greater than a first burst length when the first memory request is identified as the PIM request,
schedule the memory request by applying the first burst length when the first memory request is not identified as the PIM request, and
provide the first memory request to the RAM.

2. The PIM computing system of claim 1 , wherein the first burst length corresponds to a cache-line size on an external path for transmitting data, and the second burst length corresponds to a size of pages used for managing a memory of the DRAM.

3. The PIM computing system of claim 2 , wherein the second burst length is an integer multiple of the first burst length.

4. The PIM computing system of claim 1 , wherein when the first memory request is identified as the PIM request, the memory controller is further configured to:
receive the second memory request consecutive to the first memory request, the second memory request including a request to read data from a first bank of the RAM;
when the PIM request includes the read command and a request to read data from the first bank, providing the second memory request to the RAM after a timing constraint has elapsed, the timing constraint corresponding to the second burst length elapses from the providing of the first memory request to the RAM.

5. The PIM computing system of claim 1 , wherein the memory controller is further configured to, when the first memory request is identified as the PIM request and includes the read command:
receive the second memory request consecutive to the first memory request;
when the PIM request includes a request to read data from a first bank of the RAM and the second memory request includes a request for data reading or precharge of a second bank of the RAM different from the first bank, providing the second memory request to the RAM regardless of a timing constraint corresponding to the second burst length applied by the first memory request.

6. The PIM computing system of claim 1 , wherein the memory controller is further configured to, when the first memory request is identified as the PIM request and includes the read command:
receive the second memory request consecutive to the first memory request;
when the PIM request includes a request to read data from a first bank and the second memory request includes a request for data writing of the first bank or of a second bank of the RAM different from the first bank, provide the memory request to the RAM after a timing constraint has elapsed, the timing constraint corresponding to the second burst length applied by the PIM request and a preset timing constraint for transition from read to write.

7. The PIM computing system of claim 1 , wherein the memory controller is further configured to, when the first memory request is identified as the PIM request and includes the read command:
receive the second memory request consecutive to the first memory request;
when the PIM request includes a request to read data from a first bank and the second memory request includes a request for precharge of the first bank, provide the second memory request to the RAM after a timing constraint has elapsed, the timing constraint corresponding to the second burst length applied by the PIM request and a preset timing constraint for transition from read to precharge.

8. The PIM computing system of claim 1 , wherein the memory controller comprises:
a PIM interface unit configured to register PIM address information for identifying the PIM request, to compare an address requested by a memory request received from the outside of the memory controller with the PIM address information, and to provide a PIM request identification signal obtained by identifying whether the memory request corresponds to the PIM request;
a request queue unit configured to transmit the memory request received from the outside of the memory controller and the PIM request identification signal; and
a scheduler configured to apply the first burst length to the memory request when the first memory request is a general memory request for reading data, to apply the second burst length when the first memory request is identified by the PIM request identification signal as the PIM request and the PIM request includes the read command, and to schedule transmission of the memory request using the applied burst length.

9. The PIM computing system of claim 8 , wherein the PIM interface unit comprises:
a control register set configured to register the PIM address information of PIM operands for the PIM operation; and
a PIM request identification unit configured to provide the PIM request identification signal obtained by identifying the PIM request when the address requested by the memory request received from the outside corresponds to the PIM address information.

10. The PIM computing system of claim 9 , wherein the control register set further includes burst length information for each of the PIM operands,
wherein the PIM interface unit provides the scheduler with the burst length information of the PIM operand corresponding to the PIM request, and
wherein the scheduler applies the corresponding burst length information to the PIM request corresponding to the PIM request identification signal.

11. The PIM computing system of claim 8 , wherein the PIM interface unit comprises:
a control register set including the PIM address information of PIM operands for the PIM operation and valid information of the PIM operands; and
a PIM request identification unit configured to provide the PIM request identification signal obtained by identifying the PIM request when the address requested by the memory request received from the outside corresponds to the PIM address information, the PIM operand corresponding to the PIM address information is valid, and the memory request corresponds to a read command or a write command.

12. The PIM computing system of claim 1 , wherein the RAM comprises:
an address latch configured to store address information in response to the memory request and the PIM request;
a command latch configured to store command information in response to the memory request and the PIM request;
a memory configured to store the data; and
a PIM interface unit configured to receive the address information and the command information corresponding to the PIM request, to identify the PIM request using the address information and the command information, and to perform the PIM operation using the memory in response to the PIM request.

13. The PIM computing system of claim 12 , wherein the PIM interface unit comprises:
a control register set including the PIM address information of PIM operands for the PIM operation and valid information of the PIM operands; and
a PIM request identification unit configured to set a first matching flag for a corresponding bank address when a row address requested by the memory request and the PIM request corresponds to row address information of the PIM address information and the operand corresponding to the PIM address information is valid, to activate a second matching flag for a selected bank

Assignees

• Sk Hynix Inc
• Univ Korea Res & Bus Found

Inventors

• Kim Seon Wook
• Kim Chang Hyun
• Lee Won Joon

Classifications

• G06F3/0613 Primary

  in relation to throughput · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F15/7821 Primary

  Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title