Device, method and system to supplement a skewed cache with a victim cache

Patent metadata

Field	Value
Publication number	US-12001346-B2
Application number	US-202017127786-A
Country	US
Kind code	B2
Filing date	Dec 18, 2020
Priority date	Dec 18, 2020
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

Techniques and mechanisms for a victim cache to operate in conjunction with a skewed cache to help mitigate the risk of a side-channel attack. In an embodiment, a first line is evicted from a skewed cache, and moved to a victim cache, based on a message indicating that a second line is to be stored to the skewed cache. Subsequently, a request to access the first line results in a search of both the victim cache and sets of the skewed cache which have been mapped to an address corresponding to the first line. Based on the search, the first line is evicted from the victim cache, and reinserted in the skewed cache. In another embodiment, reinsertion of the first line in the skewed cache includes the first line and a third line being swapped between the skewed cache and the victim cache.

First claim

What is claimed is:

1. An integrated circuit comprising:
first circuitry to:
receive a first message which indicates a first address which corresponds to a first line of data; and
identify a first location of a skewed cache based on the message;

second circuitry coupled to the first circuitry, wherein, based on the first message, the second circuitry is to:
move a second line from the first location to a second location of a second cache; and
store the first line to the first location;

wherein the first circuitry is further to receive a second message which indicates a second address which corresponds to the second line; and
wherein the second circuitry is further to move the second line from the second location to the skewed cache based on the second message.

2. The integrated circuit of claim 1 , wherein the second circuitry to move the second line from the second location to the skewed cache comprises the second circuitry to swap the second line and a third line between the skewed cache and the second cache.

3. The integrated circuit of claim 2 , wherein the second line and the third line are swapped based on a valid state of the third line.

4. The integrated circuit of claim 1 , wherein, based on the first message, the second circuitry is further to evict a third line from the second location to a memory before the second circuitry is to move the second line from the first location to the second location.

5. The integrated circuit of claim 4 , wherein the second circuitry is to evict the third line based on a valid state of the third line.

6. The integrated circuit of claim 1 , wherein the second circuitry is to move the second line to the second location based on a valid state of the second line.

7. The integrated circuit of claim 1 , further comprising:
third circuitry to determine, based on the first address and a first plurality of key values, first indices which correspond to different respective sets of the skewed cache;

wherein the first circuitry is to identify the first location based on the first indices; and
wherein the third circuitry is further to determine second indices, after the second circuitry is to store the first line to the first location, which correspond to different respective sets of the skewed cache, the second indices based on the first address and a second plurality of key values.

8. A processor comprising:
a skewed cache;
a victim cache;
first circuitry coupled to the skewed cache and the victim cache, the first circuitry to move a first line from the skewed cache to the victim cache based on either one of:
a request to cache a second line; or
a miss of a search of the skewed cache and the victim cache; and

second circuitry coupled to the skewed cache and the victim cache, the second circuitry to swap the second line with a third line between the skewed cache and the victim cache based on a request to access the second line.

9. The processor of claim 8 , wherein the second line and the third line are swapped based on a valid state of the third line.

10. The processor of claim 8 , wherein, based on either one of:
the request to cache the second line; or
the miss of the search of the skewed cache and the victim cache; and

wherein the second circuitry is further to evict a fourth line from the victim cache to a memory before the first circuitry is to move the first line from the skewed cache to the victim cache.

11. The processor of claim 10 , wherein the second circuitry is to evict the fourth line based on a valid state of the fourth line.

12. The processor of claim 8 , wherein the second circuitry is to move the first line to the victim cache based on a valid state of the first line.

13. The processor of claim 8 , further comprising:
third circuitry to determine first indices which correspond to different respective sets of the skewed cache;

wherein the first circuitry is to identify a first location based on the first indices; and
wherein the third circuitry is further to determine second indices, after the second line is to be cached to the skewed cache, which correspond to different respective sets of the skewed cache, the second indices based on a first address and a second plurality of key values.

14. A system comprising:
an integrated circuit (IC) chip comprising:
first circuitry to:
receive a first message which indicates a first address which corresponds to a first line of data; and
identify a first location of a skewed cache based on the message;

second circuitry coupled to the first circuitry, wherein, based on the first message, the second circuitry is to:
move a second line from the first location to a second location of a second cache; and
store the first line to the first location;

wherein the first circuitry is further to receive a second message which indicates a second address which corresponds to the second line; and
wherein the second circuitry is further to move the second line from the second location to the skewed cache based on the second message; and
a display device coupled to the IC chip, the display device to display an image based on a signal communicated with the IC chip.

15. The system of claim 14 , wherein the second circuitry to move the second line from the second location to the skewed cache comprises the second circuitry to swap the second line and a third line between the skewed cache and the second cache.

16. The system of claim 15 , wherein the second line and the third line are swapped based on a valid state of the third line.

17. The system of claim 14 , wherein, based on the first message, the second circuitry is further to evict a third line from the second location to a memory before the second circuitry is to move the second line from the first location to the second location.

18. The system of claim 17 , wherein the second circuitry is to evict the third line based on a valid state of the third line.

19. The system of claim 14 , wherein the second circuitry is to move the second line to the second location based on a valid state of the second line.

20. The system of claim 14 , the IC chip further comprising:
third circuitry to determine, based on the first address and a first plurality of key values, first indices which correspond to different respective sets of the skewed cache;
wherein the first circuitry is to identify the first location based on the first indices; and
wherein the third circuitry is further to determine second indices, after the second circuitry is to store the first line to the first location, which correspond to different respective sets of the skewed cache, the second indices based on the first address and a second plurality of key values.

Assignees

• Intel Corp

Inventors

• Unterluggauer Thomas
• Alameldeen Alaa
• Constable Scott
• Liu Fangfei
• Mckeen Francis
• Rozas Carlos
• Trikalinou Anna

Classifications

• G06F12/14 Primary

  Protection against unauthorised use of memory {or access to memory} · CPC title

• G06F12/121

  using replacement algorithms · CPC title

• G06F2212/1052

  Security improvement · CPC title

• G06F21/72 Primary

  in cryptographic circuits · CPC title

• H04L9/003 Primary

  for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA] · CPC title