Vector fetch bus error handling

Patent metadata

Field	Value
Publication number	US-12001270-B2
Application number	US-202218075458-A
Country	US
Kind code	B2
Filing date	Dec 6, 2022
Priority date	Dec 7, 2021
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

A computer system includes a non-transitory computer-readable memory to store (a) a vector table including an exception vector pointing to an exception handler and (b) a vector fail address of a vector fetch bus error handler, and a processor to identify an exception, initiate an exception vector fetch in response to the identified exception to read the exception vector from the vector table, identify a vector fetch bus error associated with the exception vector fetch, access the vector fail address of the vector fetch bus error handler in response to the vector fetch bus error, and execute the vector fetch bus error handler.

First claim

The invention claimed is:

1. A computer system including:
non-transitory computer-readable memory to store:
a vector table including an exception vector pointing to an exception handler; and
a vector fail address of a vector fetch bus error handler; and

a processor to:
identify an exception;
in response to the identified exception, initiate an exception vector fetch to read the exception vector from the vector table;
identify a vector fetch bus error associated with the exception vector fetch;
in response to the vector fetch bus error;
set a vector fail status flag in a status register;
access the vector fail address of the vector fetch bus error handler; and
identify the vector fail status flag set in the status register, and in response, execute the vector fetch bus error handler to perform a vector fetch bus error recovery operation.

2. The computer system of claim 1 , wherein:
the exception handler comprises a bus error handler; and
the exception comprises a bus error.

3. The computer system of claim 2 , wherein the bus error comprises the vector fetch bus error handler.

4. The computer system of claim 2 , wherein the vector fetch bus error handler is separate from the bus error handler.

5. The computer system of claim 1 , wherein the non-transitory computer-readable memory comprises flash memory to store the vector table.

6. The computer system of claim 1 , wherein the non-transitory computer-readable memory comprises a register to store the vector fail address of the vector fetch bus error handler.

7. The computer system of claim 1 , wherein the non-transitory computer-readable memory comprises a special function register of the processor to store the vector fail address of the vector fetch bus error handler.

8. A method, comprising:
identifying, by a processor, an exception;
in response to the identified exception, initiating, by the processor, an exception vector fetch to read an exception vector from a vector table stored in non-transitory computer-readable memory;
identifying, by the processor, a vector fetch bus error associated with the exception vector fetch; and
in response to the vector fetch bus error:
setting, by the processor, a vector fail status flag in a status register;
accessing, by the processor, a vector fail address stored in non-transitory computer-readable memory, the vector fail address pointing to a vector fetch bus error handler; and
identifying, by the processor, the vector fail status flag set in the status register, and in response, executing, by the processor, the vector fetch bus error handler to perform a vector fetch bus error recovery operation.

9. The method of claim 8 , wherein:
the exception comprises a bus error; and
the exception vector points to a bus error handler.

10. The method of claim 9 , wherein the bus error handler comprises the vector fetch bus error handler.

11. The method of claim 10 , comprising:
prior to identifying the exception:
identifying a non-vector fetch bus error, the non-vector fetch bus error comprising a bus error unrelated to a vector fetch; and
effecting a first execution of the bus error handler including executing a first recovery operation associated with the non-vector fetch bus error;

wherein executing the vector fetch bus error handler in response to the vector fetch bus error comprises executing a second recovery operation associated with the vector fetch bus error, wherein the second recovery operation is different than the first recovery operation.

12. The method of claim 9 , wherein the vector fetch bus error handler is separate from the bus error handler.

13. The method of claim 8 , wherein accessing, by the processor, the vector fail address stored in non-transitory computer-readable memory comprises accessing the vector fail address from a register of the processor.

14. A method, comprising:
storing a reset address in a user-configurable special function register;
wherein the reset address in the user-configurable special function register is replaceable with a user-specified vector fail address in response to a user input;
identifying, by a processor, an exception;
in response to the identified exception, initiating, by the processor, an exception vector fetch to read an exception vector from a vector table stored in non-transitory computer-readable memory;
identifying, by the processor, a vector fetch bus error associated with the exception vector fetch; and
in response to the identified vector fetch bus error:
accessing, by the processor, user-configurable special function register;
if the accessed special function register stores the user-specified vector fail address pointing to the vector fetch bus error handler, accessing and executing the vector fetch bus error handler; and
if the accessed special function register stores the reset address, accessing the reset address and resetting the processor.

15. The method of claim 14 , wherein:
the exception comprises a bus error; and
the exception vector points to a bus error handler.

16. The method of claim 15 , wherein the bus error handler comprises the vector fetch bus error handler.

17. The method of claim 14 , wherein the vector fetch bus error handler is separate from the bus error handler.

Assignees

• Microchip Tech Inc

Inventors

• Catherwood Michael
• Mickey David

Classifications

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/0745 Primary

  in an input/output transactions management context (input/output processing in general G06F13/00) · CPC title

• G06F9/30101 Primary

  Special purpose registers · CPC title

• G06F9/30116

  Shadow registers, e.g. coupled registers, not forming part of the register space · CPC title