Device under test (DUT) measurement circuit having harmonic minimization

Patent metadata

Field	Value
Publication number	US-12000892-B2
Application number	US-202217589779-A
Country	US
Kind code	B2
Filing date	Jan 31, 2022
Priority date	Feb 25, 2021
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

A circuit configured to: generate a reference clock signal; generate an excitation signal at a target frequency having a period that is a first integer number of cycles of the reference clock signal; update a driver circuit at an update frequency having a period that is a second integer number of cycles of the reference clock signal; digitize sense signals resulting from the excitation signal at a frequency having a period that is a third integer number of cycles of the reference clock signal; identify a fourth integer number of sense signal samples; optionally utilize an excitation control signal having a period that is a fifth integer number of cycles of the reference clock signal; and minimize harmonics at the target frequency of the excitation signal based on the first integer number, the second integer number, the third integer number, the fourth integer number, and possibly the fifth integer number.

First claim

What is claimed is:

1. A circuit comprising:
a driver circuit having a clock input, a first frequency control input, and a driver output, the driver output coupled to a device under test (DUT) terminal;
a DUT parameter circuit having a processing input, a second frequency control input, and a DUT parameter output, the processing input coupled to the DUT terminal; and
a control circuit having a first frequency control output and a second frequency control output, the first frequency control output coupled to the first frequency control input, and the second frequency control output coupled to the second frequency control input.

2. The circuit of claim 1 , wherein:
the driver circuit is configured to:
receive a reference clock signal at the clock input; and
responsive to a first control signal at the first frequency control input, generate an
excitation signal at a target frequency having a period that is a first integer
number of cycles of the reference clock signal;

the control circuit has a third frequency control output and a fourth frequency control output;
the circuit further comprises an update circuit having a third frequency control input coupled to the third frequency control output, the update circuit configured to, responsive to a second control signal at the third frequency control input, update the driver circuit at an update frequency having a period that is a second integer number of cycles of the reference clock signal; and
the DUT parameter circuit has a fourth frequency control input coupled to the fourth frequency control output and includes:
an analog-to-digital converter (ADC) configured to:
receive sense signals at the DUT terminal; and
responsive to a third control signal at the second frequency control input, digitize the sense signals at a frequency having a period that is a third integer number of cycles of the reference clock signal to produce sense signal samples; and

a data selection circuit configured to, responsive to a fourth control signal at the fourth frequency control input, identify a set of sense signal samples, the set having a fourth integer number of samples; and
a parameter estimator circuit configured to provide a DUT parameter at the DUT parameter output based on the set of sense signal samples.

3. The circuit of claim 2 , wherein:
the control circuit has a fifth frequency control output;
the driver circuit includes a pulse-width modulation (PWM) controller; and
the circuit further comprises an excitation signal generator having a fifth frequency control input and a generator output, the fifth frequency control input coupled to the fifth frequency control output, the PWM controller coupled to the driver circuit, and the excitation signal generator configured to, responsive to a fifth control signal at the fifth frequency control input, provide an excitation control signal to the PWM controller, the excitation control signal having a frequency having a period that is a fifth integer number of cycles of the reference clock signal.

4. The circuit of claim 3 , wherein the excitation signal generator is configured to generate the excitation control signal to provide single-tone excitations and multi-tone excitations.

5. The circuit of claim 3 , wherein the control circuit is configured to minimize harmonics at the target frequency of the excitation signal based on a linear congruence of the form

n
⁢
k

=

(

k
-

p
⁢

S
⁢
N

T

-

m
⁢

S
⁢
N

P

)

⁢

(

mod
⁢

N

)

,

where k is the frequency index of the excitation signal, S is the third integer number, N is the fourth integer number of sense signal samples, S*N/k is the first integer number, T is the second integer number, P is the fifth integer number, p is an integer, m is an integer, and n is an integer.

6. The circuit of claim 3 , wherein the first, second, third and fifth integers are selected to maximize an approximate Signal-to-Interference-plus-Noise Ratio (SINR) for the sense signals.

7. The circuit of claim 3 , wherein a ratio of a product of a third and fourth integer numbers to the first integer number is an integer that is relatively prime to the fifth integer number; and the third integer number is relatively prime to the fifth integer number and relatively prime to the ratio of the product of the third and fourth integer numbers to the first integer number.

8. The circuit of claim 3 , wherein a ratio of a product of the third and fourth integer numbers to the first integer number is an integer that is relatively prime to the fifth integer number, and the third integer number is a prime number.

9. The circuit of claim 3 , wherein the sense signals indicate voltage across a battery unit and current through the battery unit, and the DUT parameter is impedance of the battery unit.

10. The circuit of claim 1 , wherein the driver circuit includes a digital-to-analog converter (DAC) having an output coupled to the driver output.

11. The circuit of claim 3 , wherein the update circuit includes a switch coupled between the excitation signal generator and the PWM controller, the switch having a control terminal coupled to the fifth frequency control input.

12. The circuit of claim 10 , further comprising a current source coupled to the DUT terminal, the current source having a control terminal coupled to the driver output.

13. A system comprising:
a measurement circuit including:
a driver circuit having a clock input, a first frequency control input, and a driver output, the driver output coupled to a device under test (DUT) terminal;
a DUT parameter circuit having a processing input, a second frequency control input, and a DUT parameter output, the processing input coupled to the DUT terminal; and
a control circuit having a first frequency control output and a second frequency control output, the first frequency control output coupled to the first frequency control input, and the second frequency control output coupled to the second frequency control input.

14. The system of claim 13 , wherein:
the driver circuit is configured to:
receive a reference clock signal at the clock input; and
responsive to a first control signal at the first frequency control input, generate an excitation signal at a target frequency having a period that is a first integer number of cycles of the

Assignees

• Texas Instruments Inc

Inventors

• Sestok Iv Charles Kasimer
• Magee David Patrick

Classifications

• G01R31/31922 Primary

  Timing generation or clock distribution (G01R31/3191 takes precedence) · CPC title

• G01R31/3167

  Testing of combined analog and digital circuits {(testing ADC's H03M1/1071)} · CPC title

• G01R31/31924

  Voltage or current aspects, e.g. driver, receiver · CPC title

• H03M1/0629

  Anti-aliasing · CPC title

• H03M1/1071

  Measuring or testing · CPC title