Display substrate, fabricating method thereof and display panel

Patent metadata

Field	Value
Publication number	US-11997891-B2
Application number	US-202017259465-A
Country	US
Kind code	B2
Filing date	Mar 24, 2020
Priority date	Mar 24, 2020
Publication date	May 28, 2024
Grant date	May 28, 2024

Abstract

Provided is display substrate, including driving circuit board, and first electrode layer, insulating layer, second electrode layer, isolation layer, transparent conductive layer sequentially stacked thereon. Driving circuit board includes pixel and bonding regions. First electrode layer includes first sub-portion in bonding region and second sub-portion in pixel region. Insulating and isolation layers are partially cover bonding and pixel regions. Insulating layer has first via hole in area corresponding to first sub-portion. Isolation layer has second via hole in the area. Axes of first and second via holes coincide, first sub-portion is exposed at first and second via holes. Second electrode layer is in pixel region, coupled to second sub-portion through third via hole in area corresponding to second sub-portion. Isolation layer has fourth via hole in area corresponding to second electrode layer. Transparent conductive layer is in pixel region, coupled to second electrode layer through fourth via hole.

First claim

What is claimed is:

1. A method for fabricating a display substrate, comprising:
fabricating a driving circuit board;
sequentially fabricating, on the driving circuit board, a first electrode layer, an insulating layer with a first via hole and a third via hole, a second electrode layer, an isolation layer with a fourth via hole, and a transparent conductive layer; and
forming a second via hole in the isolation layer,
wherein the driving circuit board comprises a pixel region and a bonding region;
fabricating the first electrode layer comprises fabricating a first sub-portion in the bonding region and a second sub-portion in the pixel region, the first sub-portion being configured to be bound to and coupled with a peripheral circuit board, and the second sub-portion being coupled to a pixel circuit in the driving circuit board;
fabricating the insulating layer comprises forming the insulating layer in both the bonding region and the pixel region, the first via hole being provided in an area of the insulating layer corresponding to the first sub-portion and the third via hole being provided in an area of the insulating layer corresponding to the second sub-portion;
fabricating the second electrode layer comprises forming the second electrode layer in the pixel region, the second electrode layer being formed to be coupled to the second sub-portion through the third via hole;
fabricating the isolation layer comprises forming the isolation layer in both the bonding region and the pixel region, the fourth via hole being provided in an area of the isolation layer corresponding to the second electrode layer, the second via hole being provided in an area of the isolation layer corresponding to the first sub-portion, wherein axes of the first and second via holes coincide, and the first sub-portion is exposed at the first and second via holes; and
fabricating the transparent conductive layer comprises forming the transparent conductive layer in the pixel region, the transparent conductive layer being formed to be coupled to the second electrode layer through the fourth via hole,
wherein the isolation layer is fabricated after the fabrication of the second electrode layer and before the fabrication of the transparent conductive layer, and the second via hole is formed after the fabrication of the transparent conductive layer.

2. The method of claim 1 , wherein in the bonding region, the isolation layer is configured to cover a sidewall of the first via hole.

3. The method of claim 2 , wherein in the bonding region, the isolation layer is configured to further extend to cover a part of the insulating layer surrounding the first via hole.

4. The method of claim 2 , wherein in the bonding region, the isolation layer is configured to further extend to cover the insulating layer in addition to covering the first via hole.

5. The method of claim 1 , wherein an orthographic projection of the transparent conductive layer on the driving circuit board coincides with an orthographic projection of the second electrode layer on the driving circuit board.

6. The method of claim 1 , wherein an orthographic projection of the second electrode layer on the driving circuit board at least partially overlaps an orthographic projection of the second sub-portion on the driving circuit board.

7. The method of claim 1 , wherein a surface of the second electrode layer away from the driving circuit board is flush with a surface of the insulating layer away from the driving circuit board.

8. The method of claim 1 , wherein the first electrode layer comprises a first metal layer, and a material of the first metal layer comprises aluminum.

9. The method of claim 8 , wherein the first electrode layer further comprises a first protective layer on a side of the first metal layer away from the insulating layer.

10. The method of claim 9 , wherein the first electrode layer further comprises a second protective layer on a side of the first metal layer close to the insulating layer.

11. The method of claim 10 , wherein the first protective layer comprises at least one of a first sub-protective layer and a second sub-protective layer; the second protective layer comprises at least one of a first sub-protective layer and a second sub-protective layer; the first sub-protective layer and the second sub-protective layer of the first protective layer are sequentially stacked in a direction away from the first metal layer, and the first sub-protective layer and the second sub-protective layer of the second protective layer are sequentially stacked in a direction away from the first metal layer; and
a material of the first sub-protective layer of each of the first protective layer and the second protective layer comprises titanium, and a material of the second sub-protective layer of each of the first protective layer and the second protective layer comprises titanium nitride.

12. The method of claim 1 , wherein the second electrode layer comprises a second metal layer, and a material of the second metal layer comprises aluminum.

13. The method of claim 12 , wherein the second electrode layer further comprises a third protective layer on a side of the second metal layer close to the insulating layer.

14. The method of claim 13 , wherein the third protective layer comprises at least one of a first sub-protective layer and a second sub-protective layer; the first sub-protective layer and the second sub-protective layer are sequentially stacked in a direction away from the second metal layer; and
a material of the first sub-protective layer comprises titanium, and a material of the second sub-protective layer comprises titanium nitride.

15. The method of claim 1 , wherein the isolation layer is made of an inorganic insulating material.

16. The method of claim 15 , wherein the isolation layer has a thickness from 200 Å to 2000 Å.

17. The method of claim 1 , wherein the transparent conductive layer is made of a semiconductor metal oxide material.

18. The method of claim 17 , wherein the transparent conductive layer has a thickness from 200 Å to 2000 Å.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Liu Li
• Lu Pengcheng
• Shi Rongrong
• Tian Yuanlan
• Bai Xiao
• Zhang Dacheng

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/124 Primary

  Insulating layers formed between TFT elements and OLED elements · CPC title

• H10K71/00

  Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title

• H10K59/1201

  Manufacture or treatment · CPC title