Hermetically sealed isolated OLED pixels

Patent metadata

Field	Value
Publication number	US-11997866-B2
Application number	US-202017136404-A
Country	US
Kind code	B2
Filing date	Dec 29, 2020
Priority date	Mar 27, 2014
Publication date	May 28, 2024
Grant date	May 28, 2024

Abstract

A novel thin film encapsulated OLED panel architecture and a method for making the panels with improved shelf life is disclosed. The OLED panel consists of a plurality of OLED pixels; each OLED pixel is individually hermetically sealed and isolated from its neighboring pixels. The organic stack of the OLED pixel is contained within its own hermetically sealed structure, achieved by making the structure on a barrier coated substrate and using a first barrier material as the grid and a second barrier for encapsulating the entire OLED pixel. The first barrier material provides the edge seal while the second barrier disposed over the pixel provides protection from top down moisture diffusion. By isolating and hermetically sealing individual pixels; any damage such as moisture and oxygen ingress due to defects or particles, delamination, cracking etc. can be effectively contained within the pixel thereby protecting other pixels in the panel.

First claim

We claim:

1. A method of fabricating an organic light emitting device (OLED) comprising:
forming a first barrier element over a substrate to provide an insulating grid for an OLED pixel disposed over the substrate;
forming a plurality of OLED pixels over the substrate, wherein each respective OLED pixel is formed over the substrate within a boundary of the first barrier element, such that the first barrier element surrounds the OLED pixel; and
forming a second barrier element over the OLED pixel and first barrier element,
wherein the first barrier element provides an edge seal for each respective OLED pixel, and the second barrier element encapsulates the OLED pixel to provide a top seal;
wherein the first vapor barrier element is inverted to form a shadow mask for OLED pixel isolation from the first vapor barrier element during formation.

2. The method of claim 1 , wherein the first barrier element is formed over the substrate by a vacuum deposition, including one or more of a sputtering, chemical vapor deposition, evaporation, sublimation, atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD) and plasma assisted atomic layer deposition operation, and combinations thereof.

3. The method of claim 2 , wherein patterning of the first barrier element is performed during a period selected from the group consisting of,
during deposition, using a single or plurality of shadow masks to obtain a desired grid profile,
during post-deposition, using photolithography, and
during post-deposition, using one or more of a wet chemical etching and dry etching, wherein dry etching includes non-plasma based etching, plasma based etching and ion beam etching.

4. The method of claim 2 , wherein the first barrier element is formed over the substrate by a sputtering deposition and either:
sputtering targets of different compositions are used; or
two targets of same composition are used with different reactive gases.

5. The method of claim 2 , wherein the first barrier element is formed over the substrate by PECVD using:
a plurality of types of precursors and/or reactive gasses; and/or
a plurality of types of deposition sources.

6. The method of claim 1 , wherein the first barrier element comprises a barrier material selected from the group consisting of:
an amorphous or polycrystalline material that includes one or more of: a metal oxide, metal nitride, metal oxynitride, metal carbide and metal oxyboride,
multiple alternate layers of SiO x N y /SiO x C y deposited at room temperature by plasma enhanced chemical vapor deposition (PECVD),
a single hybrid barrier layer deposited by plasma enhanced chemical vapor deposition (PECVD) of an organic precursor with a reactive gas,
a hybrid material comprising inorganic SiO 2 and polymeric silicone deposited at room temperature, and
a hybrid barrier material comprising SiO x C y H z ; and
wherein the substrate is comprised of a flexible polymer material including one or more of a poly carbonate material, a polymeric material, a polyethylene terephthalate (PET) material and a polyethylene naphthalate (PEN) material.

7. The method of claim 1 , wherein each respective OLED pixel comprises a stack having a cathode layer, an organic layer and an anode layer,
wherein each stack is patterned and surrounded by the first barrier element to isolate at least one of the organic layer of the respective OLED pixel from an organic layer of adjacent stacks, the cathode layer of the respective OLED pixel from a cathode layer of adjacent stacks, and the anode layer of the respective OLED pixel from an anode layer of adjacent stacks.

8. The method of claim 7 , wherein patterning of the stack is performed during one or more of deposition using vacuum thermal evaporation (VTE), organic vapor phase deposition (OVPD) through a shadow mask, ink jet printing, nozzle printing, organic vapor jet printing (OVJP), thermal jet printing (T-JET) and laser induced thermal imaging (LITI), and post-deposition using plasma etching through shadow masks.

9. The method of claim 7 , wherein patterning of the stack is performed using inverted first barrier elements as a mask.

10. The method of claim 1 , wherein the device is flexible.

11. The method of claim 1 , wherein at least one of the substrate, first barrier element and second barrier element comprise an impact resistant transparent structure.

Assignees

• Universal Display Corp

Inventors

• Harikrishna Mohan Siddharth
• Quinn William E
• Ma Ruiqing
• Krall Emory
• Walski Luke

Classifications

• H10K50/813

  characterised by their shape · CPC title

• H10K50/8426 Primary

  Peripheral sealing arrangements, e.g. adhesives, sealants · CPC title

• H10K50/82

  Cathodes · CPC title

• H10K50/844

  Encapsulations · CPC title

• H10K50/822

  characterised by their shape · CPC title