Method for manufacturing semiconductor structure and semiconductor structure

Patent metadata

Field	Value
Publication number	US-11997845-B2
Application number	US-202117503479-A
Country	US
Kind code	B2
Filing date	Oct 18, 2021
Priority date	Jan 29, 2021
Publication date	May 28, 2024
Grant date	May 28, 2024

Abstract

A method for manufacturing a semiconductor structure includes: a substrate is provided, in which the substrate is provided with a peripheral area and an array area; an insulation layer is formed on the substrate; a first mask layer with a first mask pattern is formed on the insulation layer; the insulation layer is etched by taking the first mask layer as a mask, to form a contact hole in the array area; a first electrode layer is formed; a second mask layer with a second mask pattern is formed, in which the second mask layer is arranged on the first electrode layer; and the first electrode layer and the first mask layer are etched by taking the second mask layer as a mask until the insulation layer in the array area is exposed, in which a remaining portion of the first electrode layer forms a lower electrode layer.

First claim

The invention claimed is:

1. A method for manufacturing a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a peripheral area and an array area;
forming an insulation layer on the substrate, wherein a thickness of the insulation layer in the peripheral area is less than a thickness of the insulation layer in the array area in a direction perpendicular to a surface of the substrate;
forming a first mask layer with a first mask pattern on the insulation layer;
etching the insulation layer by taking the first mask layer as a mask, to form a contact hole, which penetrates through the insulation layer, in the array area;
forming a first electrode layer, wherein the first electrode layer at least covers a surface of the first mask layer and a surface of the contact hole in the array area;
forming a second mask layer with a second mask pattern, wherein the second mask layer is arranged on the first electrode layer, and a pattern of the first mask pattern is complementary to a pattern of the second mask pattern; and
etching the first electrode layer and the first mask layer by taking the second mask layer as a mask until the insulation layer in the array area is exposed, wherein a remaining portion of the first electrode layer forms a lower electrode layer.

2. The method for manufacturing the semiconductor structure of claim 1 , wherein photomask for forming the first mask pattern is the same as photomask for forming the second mask pattern.

3. The method for manufacturing the semiconductor structure of claim 1 , wherein after the contact hole is formed and before the first electrode layer and the first mask layer are etched by taking the second mask layer as the mask, a thickness of the first mask layer in the peripheral area is greater than a thickness of the first mask layer in the array area in the direction perpendicular to the surface of the substrate.

4. The method for manufacturing the semiconductor structure of claim 3 , wherein forming the first mask layer with the first mask pattern comprises:
forming an initial first mask layer on the insulation layer;
forming a first photoresist layer with the first mask pattern on the initial first mask layer; and
etching the initial first mask layer by taking the first photoresist layer as a mask, to form the first mask layer.

5. The method for manufacturing the semiconductor structure of claim 4 , wherein etching the insulation layer by taking the first mask layer as the mask comprises: etching the insulation layer by taking the first photoresist layer and the first mask layer as a mask, wherein the first photoresist layer on the first mask layer is reserved; and removing the first photoresist layer before forming the first electrode layer.

6. The method for manufacturing the semiconductor structure of claim 5 , wherein the first electrode layer covers a surface of the first mask layer in the peripheral area, and wherein etching the first electrode layer by taking the second mask layer as the mask further comprises:
removing the first electrode layer on the first mask layer in the peripheral area.

7. The method for manufacturing the semiconductor structure of claim 6 , wherein forming the second mask layer with the second mask pattern comprises:
forming an initial second mask layer, wherein the initial second mask layer covers a surface of the first electrode layer, and a top surface of the initial second mask layer exceeds a top surface of the first electrode layer; and
patterning the initial second mask layer to form the second mask layer.

8. The method for manufacturing the semiconductor structure of claim 7 , wherein a material of the second mask layer comprises photoresist or dielectric substance comprising Si-H bonds, Si-N bonds and N-H bonds.

9. The method for manufacturing the semiconductor structure of claim 8 , wherein a property of the photoresist for forming the second mask layer is different from a property of photoresist for forming the first photoresist layer.

10. The method for manufacturing the semiconductor structure of claim 1 , wherein forming the insulation layer comprises: forming a base insulation layer on the substrate, wherein a thickness of the base insulation layer in the peripheral area is equal to a thickness of the base insulation layer in the array area in the direction perpendicular to the surface of the substrate; and
patterning the base insulation layer to form the insulation layer.

11. The method for manufacturing the semiconductor structure of claim 1 , wherein after the first electrode layer and the first mask layer are etched by taking the second mask layer as the mask, a remaining portion of the first mask layer is located on the insulation layer in the peripheral area, and the method further comprises:
removing the second mask layer;
removing a portion of the insulation layer in the array area by taking the remaining portion of the first mask layer and the lower electrode layer as a mask; and
removing the remaining portion of the first mask layer.

12. The method for manufacturing the semiconductor structure of claim 1 , wherein a material of the first mask layer is the same as a material of the first electrode layer.

13. A semiconductor structure, comprising:
a substrate provided with a peripheral area and an array area;
an insulation layer at least arranged on the substrate in the peripheral area; and
a plurality of lower electrode layers arranged in the array area, the insulation layer arranged on the substrate in the array area and arranged between adjacent lower electrode layers of the lower electrode layers, wherein a bottom and side walls of each of the lower electrode layers form a through hole, the bottom of each of the lower electrode layers abuts against the substrate, the side wall of each of the lower electrode layers away from the through hole abuts against the insulation layer, and a top surface of each of the lower electrode layers away from the substrate exceeds a top surface of the insulation layer away from the substrate; and
a thickness of the insulation layer in the peripheral area is less than a thickness of the insulation layer in the array area in a direction perpendicular to a surface of the substrate.

14. The semiconductor structure of claim 13 , wherein a height difference between the top surface of each of the lower electrode layers away from the substrate and the top surface of the insulation layer away from the substrate ranges from 10 nm to 20 nm.

Assignees

• Changxin Memory Tech Inc

Inventors

• Xia Jun
• Wan Qiang
• Xu Penghui
• Li Sen
• Zhan Kangshu
• Liu Tao

Classifications

• H10D1/716 Primary

  having vertical extensions · CPC title

• H10B12/03 Primary

  Making the capacitor or connections thereto · CPC title

• H10B12/09

  with simultaneous manufacture of the peripheral circuit region and memory cells · CPC title

• H10B12/30

  DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells · CPC title

• H10B12/50

  Peripheral circuit region structures · CPC title