Active metal fuses for DC-EOS and surge protection

Patent metadata

Field	Value
Publication number	US-11996254-B2
Application number	US-202318346298-A
Country	US
Kind code	B2
Filing date	Jul 3, 2023
Priority date	Sep 30, 2021
Publication date	May 28, 2024
Grant date	May 28, 2024

Abstract

A method comprises: forming a first metallization layer on a semiconductor die, the first metallization layer including a metal fuse; and forming a second metallization layer on the first metallization layer, in which the second metallization layer includes a thermal conductor spaced from the metal fuse, and the first metallization layer is between the second metallization layer and the semiconductor die.

First claim

What is claimed is:

1. A method, comprising:
forming a first metallization layer on a semiconductor die, the first metallization layer including a metal fuse; and
forming a second metallization layer on the first metallization layer, in which the second metallization layer includes a thermal conductor spaced from the metal fuse, and the first metallization layer is between the second metallization layer and the semiconductor die.

2. The method of claim 1 , wherein the thermal conductor overlaps at least partially with the metal fuse.

3. The method of claim 1 , further comprising forming a pre-metal dielectric (PMD) layer on the semiconductor die, wherein forming the first metallization layer on the semiconductor die includes forming the first metallization layer on the PMD layer.

4. The method of claim 1 , further comprising forming a transistor on the semiconductor die.

5. The method of claim 4 , further comprising forming a resistor in at least one of the first or second metallization layers, and connecting the resistor to a current terminal of the transistor.

6. The method of claim 5 , wherein the metal fuse has an indent, and forming the resistor includes forming at least a part of the resistor in the indent.

7. The method of claim 5 , wherein the resistor includes a serpentine portion.

8. The method of claim 5 , wherein the resistor is a first resistor formed in the first metallization layer, the transistor is a first transistor, and the current terminal is a first current terminal;
wherein the method further comprises:
forming a second transistor on the semiconductor die;
forming a second resistor in the second metallization layer; and
connecting the second resistor to a second current terminal of the second transistor.

9. The method of claim 8 , wherein the thermal conductor has an indent, and forming the second resistor includes forming at least a part of the second resistor in the indent.

10. The method of claim 8 , wherein the second resistor includes a serpentine portion.

11. The method of claim 1 , wherein the metal fuse includes a serpentine portion.

12. The method of claim 1 , further comprising:
forming conductive contacts through the first and second metallization layers; and
connecting the conductive contacts to the metal fuse.

13. The method of claim 12 , wherein the conductive contacts include Titanium Tungsten.

14. The method of claim 12 , further comprising performing wafer probe testing using the conductive contacts.

15. The method of claim 1 , further comprising forming a silicon nitride layer on the first metallization layer, wherein forming the second metallization layer includes forming the second metallization layer on the silicon nitride layer.

Assignees

• Texas Instruments Inc

Inventors

• Ramadass Yogesh K
• Radhakrishna Ujwal
• Rai Vinod Kuniganahalli

Classifications

• H01H85/048 Primary

  Fuse resistors · CPC title

• H01H85/0052

  Fusible element and series heating means or series heat dams · CPC title

• H01H85/0241

  Structural association of a fuse and another component or apparatus (switches with built-in fuses H01H9/10, spark-gap arresters H01H85/44, transformers and inductances H01F27/402, capacitors H01G2/14, lamps H01K1/66, semiconductors H10W20/493 or H10W42/80) · CPC title

• H02H9/042

  comprising means to limit the absorbed power or indicate damaged over-voltage protection device · CPC title

• H02H9/044 Primary

  Physical layout, materials not provided for elsewhere (varistors H01C7/12; spark-gaps H01T; Ovshinsky devices H10N70/00) · CPC title