Round display device having a demultiplexer located between gate stages and light emitting stages

US11996056B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11996056-B2
Application numberUS-202218088682-A
CountryUS
Kind codeB2
Filing dateDec 26, 2022
Priority dateSep 2, 2020
Publication dateMay 28, 2024
Grant dateMay 28, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display device may include a substrate including a circular display area and a non-display area, a plurality of pixels including a first pixel and a second pixel disposed on the display area of the substrate, a first sub-demux circuit connected to the first pixel and disposed on the non-display area, a second sub-demux circuit connected to the second pixel and disposed on the non-display area, a first connection line connected to the first sub-demux circuit and the second sub-demux circuit and disposed on the non-display area to transfer first and second data input signals to the first and second sub-demux circuits, and a plurality of gate stages connected to the pixels and disposed on the non-display area to transfer gate signals to the pixels. Some of the gate stages are disposed between the first sub-demux circuit and the second sub-demux circuit.

First claim

Opening claim text (preview).

What is claimed is: 1. A display device comprising: a substrate including a circular display area and a non-display area surrounding the display area; a plurality of pixels including a first pixel, a second pixel, a third pixel, and a fourth pixel disposed on the display area of the substrate; a first sub-demux circuit connected to the first pixel and disposed on the non-display area to transfer a first data output signal to the first pixel; a second sub-demux circuit connected to the second pixel and disposed on the non-display area to transfer a second data output signal to the second pixel; a third sub-demux circuit connected to the third pixel and disposed on the non-display area to transfer a third data output signal to the third pixel; a fourth sub-demux circuit connected to the fourth pixel and disposed on the non-display area to transfer a fourth data output signal to the fourth pixel; a first connection line connected to the first sub-demux circuit and the second sub-demux circuit and disposed on the non-display area to transfer a first data input signal to the first sub-demux circuit and transfer a second data input signal to the second sub-demux circuit; a second connection line connected to the third sub-demux circuit and the fourth sub-demux circuit and dispose on the non-display area to transfer a third data input signal to the third sub-demux circuit and transfer a fourth data input signal to the fourth sub-demux circuit, wherein a distance between the first sub-demux circuit and the second sub-demux circuit connected to the first connection line is different from a distance between the third sub-demux circuit and the fourth sub-demux circuit connected to the second connection line; and a plurality of gate stages connected to the pixels and disposed on the non-display area to transfer gate signals to the pixels, wherein some of the gate stages are disposed between the first sub-demux circuit and the second sub-demux circuit, and wherein another of the gate stages are disposed between the second sub-demux circuit and the third sub-demux circuit, and wherein still another of the gate stages are disposed between the third sub-demux circuit and the fourth sub-demux circuit, wherein a number of light emitting stages disposed between the first sub-demux circuit and the second sub-demux circuit is different from a number of light emitting stages disposed between the third sub-demux circuit and the fourth sub-demux circuit. 2. The display device of claim 1 , wherein the distance between the first sub-demux circuit and the second sub-demux circuit connected to the first connection line is larger than the distance between the third sub-demux circuit and the fourth sub-demux circuit connected to the second connection line. 3. The display device of claim 1 , wherein a number of the gate stages disposed between the first sub-demux circuit and the second sub-demux circuit is different from a number of the gate stages disposed between the third sub-demux circuit and the fourth sub-demux circuit. 4. The display device of claim 1 , wherein the first pixel is disposed in a first pixel column, and the second pixel is disposed in a second pixel column, and the third pixel is disposed in a third pixel column, and the fourth pixel is disposed in a fourth pixel column. 5. A display device comprising: a substrate including a circular display area and a non-display area surrounding the display area; a plurality of pixels including a first pixel, a second pixel, a third pixel, and a fourth pixel disposed on the display area of the substrate; a first sub-demux circuit connected to the first pixel and disposed on the non-display area to transfer a first data output signal to the first pixel; a second sub-demux circuit connected to the second pixel and disposed on the non-display area to transfer a second data output signal to the second pixel; a third sub-demux circuit connected to the third pixel and disposed on the non-display area to transfer a third data output signal to the third pixel; a fourth sub-demux circuit connected to the fourth pixel and disposed on the non-display area to transfer a fourth data output signal to the fourth pixel; a first connection line connected to the first sub-demux circuit and the second sub-demux circuit and disposed on the non-display area to transfer a first data input signal to the first sub-demux circuit and transfer a second data input signal to the second sub-demux circuit; a second connection line connected to the third sub-demux circuit and the fourth sub-demux circuit and dispose on the non-display area to transfer a third data input signal to the third sub-demux circuit and transfer a fourth data input signal to the fourth sub-demux circuit, wherein a distance between the first sub-demux circuit and the second sub-demux circuit connected to the first connection line is different from a distance between the third sub-demux circuit and the fourth sub-demux circuit connected to the second connection line; and a plurality of light emitting stages connected to the pixels and disposed on the non-display area to transfer light emitting signals to the pixels, wherein some of the light emitting stages are disposed between the first sub-demux circuit and the second sub-demux circuit, and wherein another of the light emitting stages are disposed between the second sub-demux circuit and the third sub-demux circuit, and wherein still another of the light emitting stages are disposed between the third sub-demux circuit and the fourth sub-demux circuit. 6. The display device of claim 5 , wherein a number of the light emitting stages disposed between the first sub-demux circuit and the second sub-demux circuit is different from a number of the light emitting stages disposed between the third sub-demux circuit and the fourth sub-demux circuit.

Assignees

Inventors

Classifications

  • forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

  • Layout of electrodes and connections · CPC title

  • Details of drivers for scan electrodes · CPC title

  • G09G3/3233Primary

    with pixel circuitry controlling the current through the light-emitting element · CPC title

  • G09G3/3275Primary

    Details of drivers for data electrodes · CPC title

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Frequently asked questions

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What does patent US11996056B2 cover?
A display device may include a substrate including a circular display area and a non-display area, a plurality of pixels including a first pixel and a second pixel disposed on the display area of the substrate, a first sub-demux circuit connected to the first pixel and disposed on the non-display area, a second sub-demux circuit connected to the second pixel and disposed on the non-display area…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3233. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 28 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 10 related publications on this page (citations in our corpus or others sharing the same primary CPC).