Method and system for executing new instructions

Patent metadata

Field	Value
Publication number	US-11995440-B2
Application number	US-202318337166-A
Country	US
Kind code	B2
Filing date	Jun 19, 2023
Priority date	Dec 29, 2020
Publication date	May 28, 2024
Grant date	May 28, 2024

Abstract

A method for executing new instructions is provided. The method is used in a processor and includes: receiving an instruction; when the received instruction is an unknown instruction, executing a conversion program by an operating system, wherein the conversion program executes the following steps: determining whether the received instruction is a new instruction; converting the received instruction into at least one old instruction when the received instruction is a new instruction; and executing the at least one old instruction.

First claim

What is claimed is:

1. A method for executing new instructions, comprising:
receiving an instruction;
decoding the received instruction with an instruction decoder;
determining whether the received instruction is an unknown instruction, based on decoded information from the instruction decoder;
when the received instruction is an unknown instruction, executing the following steps:
determining whether the received instruction is a new instruction;
converting the received instruction into at least one old instruction when the received instruction is a new instruction; and
executing the at least one old instruction.

2. The method for executing new instructions as claimed in claim 1 , wherein the received instruction is an instruction set architecture instruction, and the at least one old instruction is an instruction set architecture instruction.

3. The method for executing new instructions as claimed in claim 1 , wherein the received instruction is an x86 instruction, an ARM instruction, a RISC-V instruction, or a MIPS instruction, and the at least one old instruction is an x86 instruction, an ARM instruction, a RISC-V instruction, or a MIPS instruction.

4. The method for executing new instructions as claimed in claim 1 , further comprising:
decoding the at least one old instruction into at least one microinstruction; and
executing the at least one microinstruction.

5. The method for executing new instructions as claimed in claim 1 , further comprising:
obtaining a machine code of the received instruction according to an instruction pointer of the received instruction;
obtaining operating environment information of the received instruction; and
when the received instruction is a new instruction, converting the received instruction into at least one old instruction according to the machine code and the operating environment information.

6. The method for executing new instructions as claimed in claim 5 , further comprising:
determining whether the received instruction is a new instruction according to the machine code.

7. The method for executing new instructions as claimed in claim 5 , wherein when the received instruction is a new instruction, the method further comprises:
generating an exception when the received instruction cannot be executed in an operating mode, wherein the operating environment information comprises the operating mode.

8. The method for executing new instructions as claimed in claim 1 , further comprising:
storing the at least one old instruction into a memory or a cache.

9. The method for executing new instructions as claimed in claim 8 , further comprising:
when another received instruction is an unknown instruction:
determining whether the received instruction and the another received instruction are the same instruction when the another received instruction is a new instruction; and
obtaining the at least one old instruction from the memory or the cache when the received instruction and the another received instruction are the same instruction.

10. The method for executing new instructions as claimed in claim 1 , wherein when the received instruction is a new instruction, the method further comprises:
calculating a length of the received instruction; and
generating a first instruction pointer of a next instruction of the received instruction;
wherein the first instruction pointer is EIP+Length, wherein EIP is an instruction pointer of the received instruction, and Length is the length.

11. A system for executing new instructions, comprising:
an instruction decoder, the instruction decoder receives and decodes an instruction;
the system for executing new instructions determines whether the received instruction is an unknown instruction based on decoded information from the instruction decoder;
when the received instruction is an unknown instruction, the system for executing new instructions executes the following steps:
determining whether the received instruction is a new instruction;
converting the received instruction into at least one old instruction when the received instruction is a new instruction; and
executing the at least one old instruction.

12. The system for executing new instructions as claimed in claim 11 , wherein the received instruction is an instruction set architecture instruction, and the at least one old instruction is an instruction set architecture instruction.

13. The system for executing new instructions as claimed in claim 11 , wherein the received instruction is an x86 instruction, an ARM instruction, a RISC-V instruction, or a MIPS instruction, and the at least one old instruction is an x86 instruction, an ARM instruction, a RISC-V instruction, or a MIPS instruction.

14. The system for executing new instructions as claimed in claim 11 , wherein the system for executing new instructions further decodes the at least one old instruction into at least one microinstruction, and executes the at least one microinstruction.

15. The system for executing new instructions as claimed in claim 11 , wherein the system for executing new instructions further executes the following steps:
obtaining a machine code of the received instruction according to an instruction pointer of the received instruction;
obtaining operating environment information of the received instruction; and
when the received instruction is a new instruction, converting the received instruction into at least one old instruction according to the machine code and the operating environment information.

16. The system for executing new instructions as claimed in claim 15 , wherein the system for executing new instructions further determines whether the received instruction is a new instruction according to the machine code.

17. The system for executing new instructions as claimed in claim 15 , wherein when the received instruction is a new instruction, the system for executing new instructions further generates an exception when the received instruction cannot be executed in an operating mode, wherein the operating environment information comprises the operating mode.

18. The system for executing new instructions as claimed in claim 11 , wherein the system for executing new instructions further stores the at least one old instruction into a memory or a cache.

19. The system for executing new instructions as claimed in claim 18 , wherein when another received instruction is an unknown instruction, the system for converting instructions further executes the following steps:
determining whether the received instruction and the another received instruction are the same instruction when the another received instruction is a new instruction; and
obtaining the at least one old instruction from the memory or the cache when the received instruction and the another received instruction are the same instruction.

20. The system for executing new instructions as claimed in claim 11 , wherein when the received instruction is an unknown instruction the system for converting instructions further executes the following steps:
calculating a length of the received instruction; and
generating a first instruction pointer of a next instruction of the received instruction;
wherein the first instruction pointer is EIP+Length, wherein EIP is an instruction pointer of the received instruction, and Length is the length.

Assignees

• Shanghai Zhaoxin Semiconductor Co Ltd

Inventors

• Wang Weilin
• Yang Mengchen
• Guan Yingbing

Classifications

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/4411

  Configuring for operating with peripheral devices; Loading of device drivers · CPC title

• G06F9/542

  Event management; Broadcasting; Multicasting; Notifications · CPC title

• G06F9/4552 Primary

  Involving translation to a different instruction set architecture, e.g. just-in-time translation in a JVM · CPC title