Bus exception handling method and apparatus, electronic device and readable storage medium

Patent metadata

Field	Value
Publication number	US-11995014-B2
Application number	US-202118271658-A
Country	US
Kind code	B2
Filing date	Oct 29, 2021
Priority date	Aug 27, 2021
Publication date	May 28, 2024
Grant date	May 28, 2024

Abstract

Provided are a bus exception handling method and apparatus, an electronic device and a computer-readable storage medium. The method includes: respectively obtaining, from multiple target buses, multiple pieces of target data corresponding to the multiple target buses, where the multiple target buses include a master bus and one or more candidate buses, and the target data corresponding to the master bus is referred to as first data; determining whether the first data satisfies a bus exception condition, where the bus exception condition is a data bus marker exception condition or a data content exception condition; and in response to determining that the first data satisfies the bus exception condition, selecting a target candidate bus in a healthy state as a new master bus, and updating local bus data.

First claim

What is claimed is:

1. A bus exception handling method, comprising:
respectively obtaining, from multiple target buses, multiple pieces of target data corresponding to the multiple target buses, wherein the multiple target buses comprise a master bus and one or more candidate buses, and the target data corresponding to the master bus is referred to as first data;
determining whether the first data satisfies a bus exception condition, wherein the bus exception condition is a data bus marker exception condition or a data content exception condition; and
in response to determining that the first data satisfies the bus exception condition, selecting a target candidate bus in a healthy state as a new master bus and updating local bus data; wherein
when the bus exception condition is the data bus marker exception condition, determining whether the first data satisfies the bus exception condition comprises:
extracting current bus marker data from the first data; and
determining that the first data satisfies the data bus marker exception condition when the current bus marker data does not match the local bus data.

2. The bus exception handling method according to claim 1 , wherein when the bus exception condition is the data content exception condition, determining whether the first data satisfies the bus exception condition comprises:
determining whether the first data is consistent with target second data, wherein the one or more pieces of target data corresponding to the one or more candidate buses are referred to as second data, and the target second data is at least one piece of the second data;
in response to determining that the first data is inconsistent with the target second data, determining whether a bus variable is in an exceptional state; and
determining that the first data satisfies the data content exception condition when the bus variable is in the exceptional state.

3. The bus exception handling method according to claim 2 , wherein the bus variable is a link exception variable, and determining whether the bus variable is in the exceptional state comprises:
monitoring the master bus for a preset duration to obtain a monitoring result, wherein the preset duration is longer than a single frame length; and
determining that the link exception variable is in the exceptional state when the monitoring result is all zeros or all ones.

4. The bus exception handling method according to claim 2 , wherein the bus variable is a check exception variable, and determining whether the bus variable is in the exceptional state comprises:
counting target bits in the first data to obtain a counting result;
updating the check exception variable in response to determining that the counting result does not match check data in the first data; and
determining that the check exception variable is in the exceptional state when the check exception variable is greater than a first threshold.

5. The bus exception handling method according to claim 2 , wherein the bus variable is a type exception variable, and determining whether the bus variable is in the exceptional state comprises:
extracting type data of a frame type field from the first data;
updating the type exception variable in response to determining that the type data does not belong to standard type data; and
determining that the type exception variable is in the exceptional state when the type exception variable is greater than a second threshold.

6. The bus exception handling method according to claim 1 , further comprising:
writing the target data into a target caching location in response to determining that the first data does not satisfy the bus exception condition; and
after determining that the first data satisfies the bus exception condition, emptying the target caching location and reporting an exception when there is no target candidate bus in the healthy state.

7. An electronic device, comprising a memory and one or more processors, wherein the memory stores a computer-readable instruction, and the computer-readable instruction enables the one or more processors to execute following operations when executed by the one or more processors:
respectively obtaining, from multiple target buses, multiple pieces of target data corresponding to the multiple target buses, wherein the multiple target buses comprise a master bus and one or more candidate buses, and the target data corresponding to the master bus is referred to as first data;
determining whether the first data satisfies a bus exception condition, wherein the bus exception condition is a data bus marker exception condition or a data content exception condition; and
in response to determining that the first data satisfies the bus exception condition, selecting a target candidate bus in a healthy state as a new master bus and updating local bus data; wherein
when the bus exception condition is the data bus marker exception condition, determining whether the first data satisfies the bus exception condition comprises:
extracting current bus marker data from the first data; and
determining that the first data satisfies the data bus marker exception condition when the current bus marker data does not match the local bus data.

8. One or more non-transitory computer-readable storage media storing a computer-readable instruction, wherein the computer-readable instruction enables one or more processors to execute following operations when executed by the one or more processors:
respectively obtaining, from multiple target buses, multiple pieces of target data corresponding to the multiple target buses, wherein the multiple target buses comprise a master bus and one or more candidate buses, and the target data corresponding to the master bus is referred to as first data;
determining whether the first data satisfies a bus exception condition, wherein the bus exception condition is a data bus marker exception condition or a data content exception condition; and
in response to determining that the first data satisfies the bus exception condition, selecting a target candidate bus in a healthy state as a new master bus and updating local bus data; wherein
when the bus exception condition is the data bus marker exception condition, determining whether the first data satisfies the bus exception condition comprises:
extracting current bus marker data from the first data; and
determining that the first data satisfies the data bus marker exception condition when the current bus marker data does not match the local bus data.

9. The bus exception handling method according to claim 1 , wherein the target data is a data synchronization broadcast command, data content of which is data to be synchronized; or a request synchronization command, data content of which is unique identity information of a designated node; or taking leadership information for competing for a master node identity.

10. The bus exception handling method according to claim 9 , wherein the taking leadership information is sent on each of the multiple target buses by each CPLD in a following manner:
when detecting that a current bus does not have a master, starting, by each CPLD, a first timer;
after timing of the first timer is over, sending, by the CPLD, a taking leadership command on each of the multiple target buses, and starting, by the CPLD, a second timer;
when determining that no bus is in a non-idle state during timing of the second timer, determining, by the CPLD, that taking leadership succeeds, and sending, by the CPLD, a taking leadership succeeds command.

11. The bus exception handling method according to claim 10 , wherein detecting that the current bus does not have a master comprises:
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Assignees

• Inspur Suzhou Intelligent Technology Co Ltd

Inventors

• Jiang Bo

Classifications

• G06F13/36 Primary

  for access to common bus or bus system · CPC title

• G06F2213/0022

  Multibus · CPC title

• G06F11/221 Primary

  to test buses, lines or interfaces, e.g. stuck-at or open line faults · CPC title

• G06F11/2273

  Test methods · CPC title

• G06F11/2002

  where interconnections or communication control functionality are redundant (flexible arrangements for bus networks involving redundancy H04L12/40176) · CPC title