Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11990527-B2
Application number	US-202117514947-A
Country	US
Kind code	B2
Filing date	Oct 29, 2021
Priority date	Dec 31, 2020
Publication date	May 21, 2024
Grant date	May 21, 2024

Abstract

A semiconductor device includes an n− type layer on a first surface of the substrate, a p type region on a part of the n− type layer, a gate on the n− type layer and the p type region, a first gate protection layer on the gate and a second gate protection layer on the first gate protection layer, a source on the second gate protection layer and the p type region, and a drain on the second surface of the substrate.

First claim

What is claimed is:

1. A semiconductor apparatus comprising:
an n− type layer on a first surface of a substrate;
a p type region on a part of the n− type layer;
a gate on the n− type layer and the p type region;
a first gate protection layer on the gate;
a second gate protection layer on the first gate protection layer;
a source on the second gate protection layer and the p type region;
a drain on a second surface of the substrate; and
a gate insulating layer between the n− type layer and the gate,
wherein the gate insulating layer includes a conductive polymer in an edge region of the gate insulating layer.

2. The semiconductor device of claim 1 ,
wherein the first gate protection layer surrounds the gate,
wherein the first gate protection layer includes an upper surface portion on an upper surface of the gate and side portions on first and second sides of the gate, and
wherein the side portions of the first gate protection layer are disposed on edge regions of the gate insulating layer including a conductive polymer.

3. The semiconductor device of claim 1 ,
wherein the second gate protection layer surrounds the first gate protection layer,
wherein the second gate protection layer includes an upper surface portion on an upper surface of the first gate protection layer and side portions on first and second sides of the first gate protection layer, and
wherein the side portions of the second gate protection layer are disposed on side surfaces of the edge regions of the gate insulating layer including the conductive polymer.

4. The semiconductor device of claim 1 , wherein a lower end portion of the second gate protection layer is disposed below a lower end portion of the gate and a lower end portion of the first gate protection layer.

5. The semiconductor device of claim 1 , wherein the first gate protection layer includes Si x N y (2≤x≤4, 3≤y≤5).

6. The semiconductor device of claim 1 , wherein a thickness of the first gate protection layer is greater than or equal to about 500 Å.

7. The semiconductor device of claim 1 , wherein the second gate protection layer includes Si x O y (1≤x≤4 and 2≤y≤8), Si x N y (2≤x≤4 and 3≤y≤5), or a combination thereof.

8. The semiconductor device of claim 1 , wherein a thickness of the second gate protection layer is about 5000 Å to about 10000 Å.

9. The semiconductor device of claim 1 , wherein the substrate is an n+ type substrate.

10. The semiconductor device of claim 1 , further including an n+ region on the p type region.

11. The semiconductor device of claim 10 , wherein the n+ region is disposed between the p type region and an imaginary plane formed by lower end portions of the gate, the second gate protection layer, and the source and an edge region of the gate insulating layer.

12. A method of manufacturing a semiconductor device, the method comprising:
forming an n− type layer, and a p type region on a first surface of a substrate;
forming a gate on the n− type layer;
forming a first gate protection layer on the gate;
forming a second gate protection layer on the first gate protection layer;
forming a source on the second gate protection layer and the p type region; and
forming a drain on a second surface of the substrate,
wherein the forming of the gate includes forming a gate insulating layer on the n− type layer, forming a gate material layer on the gate insulating layer, and etching the gate material layer to form the gate,
wherein the forming of the first gate protection layer includes forming the first gate protection layer on the gate, and etching a portion of the gate insulating layer which is not protected by the first gate protection layer, using the first gate protection layer as a mask, to remove the portion of the gate insulating layer, and
wherein the gate insulating layer includes a conductive polymer by etching using an etching gas.

13. The method of claim 12 , wherein the gate material layer is etched using the etching gas including C 4 F 6 , C 4 C 8 , or a combination thereof.

14. The method of claim 12 , wherein in the removing of the portion of the gate insulating layer by etching, the p type region is partially etched to a predetermined depth of the p type region after the portion of the gate insulating layer is removed.

15. The method of claim 12 , which further includes injecting n+ ions into the p type region to form an n+ region using the first gate protection layer as a mask after etching and removing the portion of the gate insulating layer and before forming the second gate protection layer.

Assignees

• Hyundai Motor Co Ltd
• Kia Corp

Inventors

• Park Junghee
• Chun Dae Hwan
• Hong Jungyeop
• Jung Youngkyun
• Joo Nackyong

Classifications

• H10D30/66 Primary

  Vertical DMOS [VDMOS] FETs · CPC title

• H10D30/0291

  of vertical DMOS [VDMOS] FETs · CPC title

• H10D64/01

  Manufacture or treatment · CPC title

• H10D62/154

  Dispositions · CPC title

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title