Three-dimensional memory devices having isolation structure for source select gate line and methods for forming the same

Patent metadata

Field	Value
Publication number	US-11990506-B2
Application number	US-202017084346-A
Country	US
Kind code	B2
Filing date	Oct 29, 2020
Priority date	Sep 4, 2020
Publication date	May 21, 2024
Grant date	May 21, 2024

Abstract

Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, and one or more isolation structures. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). Each isolation structure surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure.

First claim

What is claimed is:

1. A three-dimensional (3D) memory device, comprising:
a substrate;
a memory stack on the substrate comprising a plurality of interleaved conductive layers and dielectric layers, an outmost one of the conductive layers toward the substrate being a source select gate line (SSG);
a plurality of channel structures each extending vertically through the memory stack; and
one or more isolation structures each surrounding at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure,
wherein a first group of the plurality of channel structures is spaced apart from the SSG and a second group of the plurality of channel structures is in direct contact with the SSG.

2. The 3D memory device of claim 1 , wherein the plurality of channel structures are disposed in a core array region and an edge region in the plan view, and the at least one channel structure is disposed in the edge region.

3. The 3D memory device of claim 2 , wherein the memory stack comprises a staircase structure, the edge region is laterally between the staircase structure and the core array region, and the at least one channel structure is disposed in an outmost column adjacent to the staircase structure in the plan view.

4. The 3D memory device of claim 2 , wherein a lateral dimension of the at least one channel structure is greater than a lateral dimension of the channel structures disposed in the core array region.

5. The 3D memory device of claim 1 , wherein a lateral distance between the SSG and the at least one channel structure is between about 40 nm and about 80 nm.

6. The 3D memory device of claim 1 , wherein each of the channel structures comprises a semiconductor plug at one end toward the substrate.

7. The 3D memory device of claim 6 , wherein one of the one or more isolation structures is laterally between the SSG and the semiconductor plug of the at least one channel structure.

8. The 3D memory device of claim 1 , wherein each of the one or more isolation structures surrounds a respective one of the at least one channel structure.

9. The 3D memory device of claim 1 , wherein one of the one or more isolation structures surrounds a plurality ones of the at least one channel structure.

10. The 3D memory device of claim 1 , wherein the one or more isolation structures comprise a dielectric.

11. The 3D memory device of claim 1 , further comprising an SSG cut coplanar with the one or more isolation structures.

12. A three-dimensional (3D) memory device, comprising:
a plurality of channel structures disposed in a core array region and an edge region in a plan view; and
a source select gate line (SSG) extending laterally across the core array region and the edge region,
wherein at least one of the channel structures in the core array region is in direct contact with the SSG, and at least one of the channel structures in the edge region is spaced apart from the SSG.

13. The 3D memory device of claim 12 , further comprising one or more isolation structures extending vertically through the SSG in the edge region, wherein the at least one channel structure in the edge region is contact with the one or more isolation structures.

14. A method for forming a three-dimensional (3D) memory device, comprising:
forming a source select gate line (SSG) sacrificial layer above a substrate;
forming an isolation structure through the SSG sacrificial layer;
forming a plurality of interleaved word line dielectric layers and word line sacrificial layers above the SSG sacrificial layer and the isolation structure;
after forming the plurality of interleaved word line dielectric layers and word line sacrificial layers, forming a first channel structure comprising a semiconductor plug extending vertically through the interleaved word line dielectric layers and word line sacrificial layers and the isolation structure; and
replacing the word line sacrificial layers and the SSG sacrificial layer with a plurality of conductive layers to form a plurality of word lines and an SSG, respectively, such that the first channel structure is spaced apart from the SSG by the isolation structure.

15. The method of claim 14 , further comprising forming a second channel structure extending vertically through the interleaved word line dielectric layers and word line sacrificial layers and the SSG sacrificial layer in a same process for forming the first channel structure, wherein the second channel structure is in contact with the SSG by replacing the word line sacrificial layers and the SSG sacrificial layer with the plurality of conductive layers to form the plurality of word lines and the SSG.

16. The method of claim 14 , further comprising sequentially forming a buffer layer and a stop layer on the SSG sacrificial layer.

17. The method of claim 16 , wherein forming the isolation structure comprises:
etching an isolation trench through the stop layer, the buffer layer, and the SSG sacrificial layer;
depositing a dielectric layer to fill the isolation trench;
planarizing the dielectric layer stopping at the stop layer; and
removing the stop layer.

18. The method of claim 14 , further comprising forming an SSG cut through the SSG sacrificial layer in a same process of forming the isolation structure.

19. The method of claim 14 , wherein the SSG sacrificial layer comprises silicon nitride, and the isolation structure comprises silicon oxide.

20. The method of claim 15 , wherein forming the first and second channel structures in the same process comprises:
simultaneously forming (i) a first channel hole extending vertically through the interleaved word line dielectric layers and word line sacrificial layers and the isolation structure, and (ii) a second channel hole extending vertically through the interleaved word line dielectric layers and word line sacrificial layers and the SSG sacrificial layer; and
simultaneously forming (i) a first semiconductor plug in a bottom portion of the first channel hole spaced apart from the SSG sacrificial layer, and (ii) a second semiconductor plug in a bottom portion of the second channel hole in contact with the SSG sacrificial layer.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Wu Jiajia
• Geng Jingjing
• Zhou Yang
• Guo Zhen
• Xiao Meng
• Zhang Hui

Classifications

• H10D62/115 Primary

  Dielectric isolations, e.g. air gaps · CPC title

• H01L29/0649 Primary

  Electricity · mapped topic

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• H10B41/10 Primary

  characterised by the top-view layout · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title