Centralized interrupt handling for chiplet processing units

Patent metadata

Field	Value
Publication number	US-11989144-B2
Application number	US-202117389994-A
Country	US
Kind code	B2
Filing date	Jul 30, 2021
Priority date	Jul 30, 2021
Publication date	May 21, 2024
Grant date	May 21, 2024

Abstract

Systems, apparatuses, and methods for implementing a centralized interrupt controller to aggregate interrupts generated across multiple semiconductor dies are disclosed. A system includes multiple interrupt sources on multiple semiconductor dies. A centralized interrupt controller on one of the semiconductor dies receives and aggregates interrupts from the multiple interrupt sources on the multiple semiconductor dies. This facilitates a single transmission point for forwarding the interrupts to the processor and operating system responsible for handling interrupts. Each interrupt source embeds an ID when conveying an interrupt to the interrupt controller. This allows the interrupt controller to differentiate between the interrupt sources and to identify which source generated a given interrupt. The interrupt controller conveys an indication of the source of the interrupt to the processor when forwarding the interrupt to the processor.

First claim

What is claimed is:

1. An apparatus comprising:
a master interrupt controller, in a first semiconductor die of a plurality of semiconductor dies on a substrate, comprising circuitry configured to:
receive, via a communication link, interrupts generated by at least:
a first interrupt source in the first semiconductor die; and
a second interrupt source in a second semiconductor die of the plurality of semiconductor dies;

in response to receiving a given interrupt, determine which of the first interrupt source and the second interrupt source generated the given interrupt; and
convey the given interrupt, with an indication of which source generated the given interrupt, to a processor for handling by the processor.

2. The apparatus as recited in claim 1 , wherein the first semiconductor die has a first identifier (ID) and wherein the second semiconductor die has a second ID different from the first ID.

3. The apparatus as recited in claim 1 , wherein the second semiconductor die comprises an interrupt controller that is disabled.

4. The apparatus as recited in claim 1 , wherein the master interrupt controller is configured to map physical initiator IDs to logical initiator IDs.

5. The apparatus as recited in claim 1 , wherein each of the first semiconductor die and the second semiconductor die is a chiplet.

6. The apparatus as recited in claim 1 , wherein the first interrupt source has a first physical initiator identifier (ID) and the second interrupt source has a second physical initiator ID different from the first physical initiator ID.

7. The apparatus as recited in claim 1 , wherein the processor comprises a mapping table which maps logical initiator IDs to guest operating system IDs.

8. A method comprising:
receiving, by a master interrupt controller in a first semiconductor die of a plurality of semiconductor dies on a substrate, interrupts from at least a first interrupt source in the first semiconductor die and a second interrupt source in a second semiconductor die;
determining which of the first interrupt source and the second interrupt source generated a given interrupt responsive to receiving the given interrupt; and
conveying the given interrupt, along with an indication of which source generated the given interrupt, to a processor for handling by the processor.

9. The method as recited in claim 8 , wherein the first semiconductor die has a first identifier (ID) and wherein the second semiconductor die has a second ID different from the first ID.

10. The method as recited in claim 9 , further comprising sending, by the first interrupt source, the first ID to the master interrupt controller with interrupts generated by the first interrupt source.

11. The method as recited in claim 8 , further comprising mapping, by the master interrupt controller, physical initiator IDs to logical initiator IDs.

12. The method as recited in claim 11 , further comprising determining, by the master interrupt controller, a logical initiator ID of a source which generates an interrupt by accessing a mapping table with a physical initiator ID received with the interrupt.

13. The method as recited in claim 8 , wherein the first semiconductor die includes a third interrupt source, wherein the first interrupt source has a first identifier (ID), wherein the second interrupt source has a second ID different from the first ID, and wherein the third interrupt source has a third ID different from the second ID and the first ID.

14. The method as recited in claim 8 , further comprising:
maintaining a mapping table which maps logical initiator IDs to guest operating system IDs; and
determining a guest operating system corresponding to the given interrupt by accessing the mapping table with a given logical initiator ID corresponding to the given interrupt.

15. A system comprising:
a plurality of semiconductor dies on a substrate; and
a master interrupt controller comprising circuitry configured to:
receive interrupts from a first interrupt source in a first semiconductor die of the plurality of semiconductor dies and a second interrupt source in a second semiconductor die of the plurality of semiconductor dies;
responsive to receiving a given interrupt, determine which of the first interrupt source and the second interrupt source generated the given interrupt; and
convey the given interrupt, along with an indication of which source generated the given interrupt, to a processor for handling by the processor.

16. The system as recited in claim 15 , wherein the first semiconductor die has a first identifier (ID) and wherein the second semiconductor die has a second ID different from the first ID.

17. The system as recited in claim 16 , wherein the first interrupt source sends the first ID to the master interrupt controller with interrupts generated by the first interrupt source.

18. The system as recited in claim 15 , wherein the master interrupt controller is configured to map physical initiator IDs to logical initiator IDs.

19. The system as recited in claim 15 , wherein the first semiconductor die and a second semiconductor die appear to a programming model as a single monolithic unit.

20. The system as recited in claim 15 , wherein the first semiconductor die includes a third interrupt source, wherein the first interrupt source has a first identifier (ID), wherein the second interrupt source has a second ID different from the first ID, and wherein the third interrupt source has a third ID different from the second ID and the first ID.

Assignees

• Advanced Micro Devices Inc

Inventors

• Dong Haikun
• Huang Zengrong
• Wang Ling-Ling
• Wu Minhua
• Gao Jie
• Liu Ruihong

Classifications

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F9/4812 Primary

  by interrupt, e.g. masked · CPC title