Array substrate, method for manufacturing same, and display device

Patent metadata

Field	Value
Publication number	US-11988927-B2
Application number	US-202117772531-A
Country	US
Kind code	B2
Filing date	Mar 9, 2021
Priority date	Apr 10, 2020
Publication date	May 21, 2024
Grant date	May 21, 2024

Abstract

Provided is an array substrate. The array substrate includes a plurality of sub-pixels; wherein a storage capacitor and an extended storage capacitor are disposed in each of the plurality of sub-pixels, the extended storage capacitor and the storage capacitor being connected in parallel; and the array substrate includes a gate electrode layer, a source and drain electrode layer, and a pixel electrode.

First claim

What is claimed is:

1. An array substrate, comprising a plurality of sub-pixels; wherein
a storage capacitor and an extended storage capacitor are disposed in each of the plurality of sub-pixels, the extended storage capacitor and the storage capacitor being connected in parallel; and
the array substrate comprises a gate electrode layer, a source and drain electrode layer, and a pixel electrode;
wherein
a first capacitor plate of the storage capacitor is the pixel electrode, and a second capacitor plate of the storage capacitor is a first electrode in the source and drain electrode layer;
a first capacitor plate of the extended storage capacitor is the pixel electrode, a second capacitor plate of the extended storage capacitor is disposed in the source and drain electrode layer, and the second capacitor plate of the extended storage capacitor is connected to the first electrode in the source and drain electrode layer;
the plurality of sub-pixels are arranged in an array, and the source and drain electrode layer comprises a plurality of data lines extending along a column direction; and
two sub-pixels in the same row of sub-pixels are disposed between two adjacent data lines, each of the two sub-pixels comprises an opening region, and second capacitor plates of extended storage capacitors of the two sub-pixels are disposed between two opening regions of the two sub-pixels.

2. The array substrate according to claim 1 , wherein the second capacitor plate of the extended storage capacitor is strip-shaped, wherein both lengths of the two strip-shaped second capacitor plates disposed in the same row of sub-pixels between the two adjacent data lines extend along the column direction, first ends of the strip-shaped second capacitor plates are connected to the corresponding first electrodes, and orthographic projections of the two strip-shaped second capacitor plates along a row direction are not overlapped with each other, the row direction being perpendicular to the column direction.

3. The array substrate according to claim 1 , wherein a capacitance of the storage capacitor ranges from 0.12 pF to 0.15 pF, and a capacitance of the extended storage capacitor and the storage capacitor connected in parallel ranges from 0.18 pF to 0.22 pF.

4. A display device, comprising an array substrate comprising a plurality of sub-pixels; wherein
a storage capacitor and an extended storage capacitor are disposed in each of the plurality of sub-pixels, the extended storage capacitor and the storage capacitor being connected in parallel; and
the array substrate comprises a gate electrode layer, a source and drain electrode layer, and a pixel electrode;
wherein a first capacitor plate of the storage capacitor is the pixel electrode, and a second capacitor plate of the storage capacitor is a first electrode in the source and drain electrode layer;
a first capacitor plate of the extended storage capacitor is the pixel electrode, a second capacitor plate of the extended storage capacitor is disposed in the source and drain electrode layer, and the second capacitor plate of the extended storage capacitor is connected to the first electrode in the source and drain electrode layer;
the plurality of sub-pixels are arranged in an array, and the source and drain electrode layer comprises a plurality of data lines extending along a column direction; and
two sub-pixels in the same row of sub-pixels are disposed between two adjacent data lines, each of the two sub-pixels comprises an opening region, and second capacitor plates of extended storage capacitors of the two sub-pixels are disposed between two opening regions of the two sub-pixels.

5. The display device according to claim 4 , wherein the second capacitor plate of the extended storage capacitor is strip-shaped, wherein both lengths of the two strip-shaped second capacitor plates disposed in the same row of sub-pixels between the two adjacent data lines extend along the column direction, first ends of the strip-shaped second capacitor plates are connected to the corresponding first electrodes, and orthographic projections of the two strip-shaped second capacitor plates along a row direction are not overlapped with each other, the row direction being perpendicular to the column direction.

6. The display device according to claim 4 , wherein a capacitance of the storage capacitor ranges from 0.12 pF to 0.15 pF, and a capacitance of the extended storage capacitor and the storage capacitor connected in parallel ranges from 0.18 pF to 0.22 pF.

7. A method for manufacturing an array substrate, the array substrate comprising a plurality of sub-pixels,
the method comprising:
successively manufacturing a gate electrode layer, a source and drain electrode layer, and a pixel electrode, and forming a storage capacitor and an extended storage capacitor in the sub-pixel, the extended storage capacitor and the storage capacitor being connected in parallel;
wherein a first capacitor plate of the storage capacitor is the pixel electrode, and a second capacitor plate of the storage capacitor is a first electrode in the source and drain electrode layer; a first capacitor plate of the extended storage capacitor is the pixel electrode, and a second capacitor plate of the extended storage capacitor is disposed in the source and drain electrode layer, and the second capacitor plate of the extended storage capacitor is connected to the first electrode in the source and drain electrode layer;
the plurality of sub-pixels are arranged in an array, and the source and drain electrode layer comprises a plurality of data lines extending along a column direction; and
two sub-pixels in the same row of sub-pixels are disposed between two adjacent data lines, each of the two sub-pixels comprises an opening region, and second capacitor plates of extended storage capacitors of the two sub-pixels are disposed between two opening regions of the two sub-pixels.

8. The method according to claim 7 , wherein the second capacitor plate of the extended storage capacitor is strip-shaped, wherein both lengths of the two strip-shaped second capacitor plates disposed in the same row of sub-pixels between the two adjacent data lines extend along the column direction, first ends of the strip-shaped second capacitor plates are connected to the corresponding first electrodes, and orthographic projections of the two strip-shaped second capacitor plates along a row direction are not overlapped with each other, the row direction being perpendicular to the column direction.

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Zhang Zhengdong
• Yang Xiaofei
• Su Lei
• Wang Limiao
• Wang Hongjun
• Meng Jia
• Hu Xiaoxu

Classifications

• G02F1/134309

  characterised by their geometrical arrangement · CPC title

• G02F1/136213 Primary

  Storage capacitors associated with the pixel electrode · CPC title

• G02F1/136209

  Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/1343

  Electrodes {(reflective electrodes G02F1/133553)} · CPC title