Display device

Patent metadata

Field	Value
Publication number	US-11988911-B2
Application number	US-202318169391-A
Country	US
Kind code	B2
Filing date	Feb 15, 2023
Priority date	Mar 7, 2017
Publication date	May 21, 2024
Grant date	May 21, 2024

Abstract

In one embodiment, a display device includes a display area, a peripheral area, scanning lines, signal lines, a first driver in the peripheral area, and a second driver in the peripheral area. The display area has an arc-shaped corner. The first driver includes first and second buffers configured to apply voltage to the scanning lines, a first shift register unit configured to control the first buffer unit, and a second shift register unit configured to control the second buffer unit. At the corner, extension directions of the first buffer unit and the first shift register unit are equal to each other. Extension directions of the second buffer unit and the second shift register unit are different from each other.

First claim

What is claimed is:

1. A display device comprising:
a first pixel row in a display area;
a second pixel row next to the first pixel row in the display area;
a first scanning line of the first pixel row;
a second scanning line of the second pixel row;
a scanning line driver including a first transistor connected to the first scanning line, and a second transistor connected to the second scanning line;
a first video signal line;
a second video signal line;
a first selector circuit connected to the first video signal line; and
a second selector circuit connected to the second video signal line,
wherein
the first scanning line extends between the first selector circuit and the second selector circuit,
the second scanning line extends between the first selector circuit and the second selector circuit, and
a first gap between the first scanning line and the second scanning line in a region between the first selector circuit and the second selector circuit is smaller than a second gap between the first scanning line and the second scanning line in the display area.

2. The display device of claim 1 , wherein
the first video signal line and the second video signal line are arrayed in a first direction in the display area,
the first scanning line and the second scanning line are arrayed in a second direction intersecting the first direction in the display area, and
the second selector circuit is displaced from the first selector circuit in the first direction and the second direction.

3. The display device of claim 2 , wherein
the first scanning line and the second scanning line extend parallel to each other in the region between the first selector circuit and the second selector circuit.

4. The display device of claim 2 , wherein
the first video signal line does not cross either of the first scanning line and the second scanning line, and
the second video signal line crosses each of the first scanning line and the second scanning line.

5. The display device of claim 2 , wherein
the first transistor and the second transistor are located outside of the display area,
the first transistor is located on an extension line of the second pixel row in the first direction, and
the second transistor is displaced from the extension line in the second direction.

6. The display device of claim 2 , wherein
the first selector circuit is connected to the second selector circuit by a connection line, and
the first scanning line and the second scanning line cross the connection line at the region between the first selector circuit and the second selector circuit.

7. The display device of claim 2 , wherein
the scanning line driver includes a first buffer circuit and a second buffer circuit,
the first buffer circuit includes the first transistor,
the second buffer circuit includes the second transistor, and
the first buffer circuit and the second buffer circuit are adjacent to each other in the second direction and are not displaced in the first direction.

8. The display device of claim 2 , wherein
the scanning line driver includes a first buffer circuit and a second buffer circuit,
the first buffer circuit includes the first transistor,
the second buffer circuit includes the second transistor, and
the first buffer circuit and the second buffer circuit are adjacent to each other in the first direction and are not displaced in the second direction.

Assignees

• Japan Display Inc

Inventors

• Koide Gen
• Noshita Shimpei
• Kitamura Junichi

Classifications

• G02F1/13306 Primary

  Circuit arrangements or driving methods for the control of single liquid crystal cells (G02F1/132, G02F1/133382 take precedence) · CPC title

• G02F1/133514

  Colour filters · CPC title

• G02F1/1337

  Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers · CPC title

• G02F1/1343

  Electrodes {(reflective electrodes G02F1/133553)} · CPC title

• G02F1/13454 Primary

  Drivers integrated on the active matrix substrate (G02F1/136277 takes precedence) · CPC title