Software PUF based on RISC-V processor for IoT security

Patent metadata

Field	Value
Publication number	US-11985261-B2
Application number	US-202217900848-A
Country	US
Kind code	B2
Filing date	Aug 31, 2022
Priority date	Jan 10, 2022
Publication date	May 14, 2024
Grant date	May 14, 2024

Abstract

Disclosed is a software PUF based on an RISC-V processor for IoT security. A 32-bit RISC-V processor is used to generate abnormal information results in an abnormal operating state under a low voltage, and the abnormal information results are used to represent the features of the 32-bit RISC-V processor; 5-bit binary data obtained by comparing the abnormal information results with normal information results has high randomness and uniqueness and it is extremely difficult to directly extract internal abnormal information result from a hardware circuit of the 32-bit RISC-V processor, so modeling attacks based on the 5-bit binary data calculated according to the abnormal information results of the 32-bit RISC-V processor are almost impossible; in addition, when the 32-bit RISC-V processor is in an abnormal operating state, the operating frequency of the 32-bit RISC-V processor is dynamically adjusted through a frequency compensation method.

First claim

What is claimed is:

1. A software PUF based on an RISC-V processor for IoT security, characterized in that comprises a 32-bit RISC-V processor, wherein a temperature sensor for monitoring an operating temperature of the 32-bit RISC-V processor and a voltage sensor for monitoring an operating voltage of the 32-bit RISC-V processor are configured in the 32-bit RISC-V processor, and the 32-bit RISC-V processor generates an output response through the following method:
(1) randomly selecting, from R instructions, four groups of instructions and four groups of operands corresponding to the four groups of instructions, wherein the four groups of instructions are all 32-bit binary data, and the four groups of operands are all 64-bit binary data;
(2) accessing a supply voltage to the 32-bit RISC-V processor, wherein the supply voltage is a normal operating voltage of the 32-bit RISC-V processor, and the 32-bit RISC-V processor enters a normal operating state under the normal operating voltage, and an operating frequency of the 32-bit RISC-V processor at this moment is a normal operating frequency; sequentially loading the four groups of operands to a general register with a load instruction, sorting the four groups of instructions in chronological order, sequentially running the four groups of instructions and the corresponding four groups of operands according to the sorting order to successively obtain four normal information results corresponding to the four groups of instructions, and storing the four normal information results in the general register, wherein the four normal information results are 32-bit binary data;
(3) decreasing the supply voltage accessed to the 32-bit RISC-V processor to 0.7V, wherein the supply voltage at this moment is an abnormal operating voltage of the 32-bit RISC-V processor, and the 32-bit RISC-V processor enters an abnormal operating state under the abnormal operating voltage;
(4) acquiring a current operating temperature of the 32-bit RISC-V processor from the temperature sensor, acquiring a current operating voltage of the 32-bit RISC-V processor from the voltage sensor, denoting the current operating temperature of the 32-bit RISC-V processor as temp cur , denoting the current operating voltage of the 32-bit RISC-V processor as V cur , and obtaining a compensatory operating frequency of the 32-bit RISC-V processor by calculation according to formula (1):

F
com

=

1

1

ln
⁢

a
temp

×

(

temp

c
⁢
u
⁢
r

-

temp
ref

)

+

1

F
ref

+

1

ln
⁢

a
vdd

×

(

V
cur

-

V
ref

)

+

1

F
ref

(
1
)

In formula (1), temp ref is a reference temperature of the 32-bit RISC-V processor ((temp ref =25° C.), V ref is a reference voltage of the 32-bit RISC-V processor (V ref =0.7V), F ref is the normal operating frequency of the 32-bit RISC-V processor, F com is the compensatory operating frequency of the 32-bit RISC-V processor, a temp is a temperature compensation coefficient of the 32-bit RISC-V processor and is determined by testing the fluctuation velocity of a delay of the 32-bit RISC-V processor with time under different temperatures, a vdd is a voltage compensation coefficient of the 32-bit RISC-V processor and is determined by testing the fluctuation velocity of the delay of the 32-bit RISC-V processor with voltage under different supply voltages, and In is a logarithmic operator;
(5) setting the operating frequency of the 32-bit RISC-V processor as the compensatory operating frequency;
(6) loading the four groups of operands to the general register again with the load instruction, then sequentially running the four groups of instructions and the corresponding four groups of operands in chronological order the same as that in Step (2) to successively obtain four abnormal information results corresponding to the four groups of instructions, and storing the four abnormal information results in the general register, wherein the four abnormal information results are 32-bit binary data;
(7) bitwise comparing the normal information results and the abnormal information results corresponding to the four groups of instructions one by one to determine error bits of the abnormal information result corresponding to each group of instructions with respect to the normal information result corresponding to the group of instructions, calculating the number of the error bits, and then converting the number of the error bits into 5-bit binary data, so that four pieces of 5-bit binary data corresponding to the four groups of instructions are obtained; and
(8) sequentially stitching the four pieces of 5-bit binary data from high bit to low bit according to a corresponding instruction running order to obtain 20-bit binary data, wherein the 20-bit binary data is t

Assignees

• Univ Wenzhou

Inventors

• Wang Pengjun
• Ni Li
• Zhang Yue Jun
• Zhou Di
• Shi Yijian

Classifications

• H04L9/3278 Primary

  using physically unclonable functions [PUF] · CPC title

• G06F21/73 Primary

  by creating or determining hardware identification, e.g. serial numbers · CPC title

• G06F11/3058

  Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206) · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• H04L2209/08

  Randomization, e.g. dummy operations or using noise · CPC title