Electronic circuit to generate a DC voltage from a wireless signal and method of manufacture

Patent metadata

Field	Value
Publication number	US-11984640-B2
Application number	US-201917274237-A
Country	US
Kind code	B2
Filing date	Sep 10, 2019
Priority date	Sep 10, 2018
Publication date	May 14, 2024
Grant date	May 14, 2024

Abstract

An electronic circuit is described, comprising: a first power rail; a second power rail; and a field effect transistor, FET, the FET comprising: a first terminal coupled directly or indirectly to the first power rail; a second terminal coupled directly or indirectly to the second power rail; a channel of semiconductive material connecting the first terminal to the second terminal; a gate terminal to which a voltage may be applied to control a conductivity of the channel, the channel providing a conduction path from the first terminal to the second terminal; and a gate dielectric arranged to insulate the gate terminal from the channel. The circuit further comprises a layer or other body of dielectric material, the gate dielectric being a first portion of the layer or other body of dielectric material. The first power rail comprises a first rail portion arranged on a first side of a second portion of the layer or other body of dielectric material, and the second power rail comprises a second rail portion arranged on a second side of the second portion of the layer or other body of dielectric material, the second side being opposite the first side. The second portion of the layer or other body of dielectric material separates the first and second rail portions and with the first and second rail portions provides a capacitance to the circuit.

First claim

The invention claimed is:

1. An electronic circuit comprising:
a first power rail;
a second power rail; and
a field effect transistor, FET, comprising:
a first terminal coupled directly or indirectly to the first power rail;
a second terminal coupled directly or indirectly to the second power rail;
a channel of semiconductive material connecting the first terminal to the second terminal;
a gate terminal to which a voltage may be applied to control a conductivity of said channel, said channel providing a conduction path from the first terminal to the second terminal; and
a gate dielectric arranged to insulate the gate terminal from said channel,

wherein said electronic circuit comprises a layer or other body of dielectric material, said gate dielectric being a first portion of the layer or other body of dielectric material, and in that the first power rail comprises a first rail portion arranged on a first side of a second portion of the layer or other body of dielectric material, and the second power rail comprises a second rail portion arranged on a second side of the second portion of the layer or other body of dielectric material, said second side being opposite said first side, whereby said second portion of the layer or other body of dielectric material separates said first and second rail portions and with said first and second rail portions providing a capacitance to said circuit.

2. The circuit in accordance with claim 1 , wherein the other body of dielectric material is a layer.

3. The circuit in accordance with claim 2 , wherein said layer has a thickness in the range 1 nm to 500 nm.

4. The circuit in accordance with claim 1 , wherein said dielectric material has a dielectric constant greater than 3.9.

5. The circuit in accordance with claim 1 , wherein said FET is a thin film transistor.

6. The circuit in accordance with claim 1 , wherein said first and second terminals and said first rail portion are each substantially flat and coplanar with one another.

7. The circuit in accordance with claim 6 , wherein said first terminal is directly connected to said first rail portion.

8. The circuit in accordance with claim 7 , wherein said first terminal and said first rail portion are respective portions of a flat layer or other body of conductive material.

9. The circuit in accordance with claim 1 , wherein said gate terminal and said second rail portion are each substantially flat and coplanar with one another.

10. The circuit in accordance with claim 1 , wherein said first rail portion is in direct contact with said first side.

11. The circuit in accordance with claim 1 , wherein said second rail portion is in direct contact with said second side.

12. The circuit in accordance with claim 1 , further comprising an antenna arranged to receive a wireless signal, rectifying means connected to the antenna and to the first and second power rails and arranged to generate a DC voltage between said first and second power rails from a received wireless signal.

13. The circuit in accordance with claim 12 , further comprising a capacitor connected between said first and second power rails to smooth said DC voltage.

14. The circuit in accordance with claim 1 , wherein the circuit comprises a layer of semiconductive material, said first and second terminals and said first rail portion are formed on a first surface of the layer of semiconductive material, said channel being provided by a portion of the layer of semiconductive material, the layer or other body of dielectric material is formed over the first and second terminals and said first rail portion, and said gate terminal and second rail portion are formed on a first surface of the layer or other body of dielectric material.

15. The circuit in accordance with claim 14 , further comprising a substrate under the layer of semiconductive material.

16. The circuit in accordance with claim 1 , further comprising a substrate and a layer of semiconductive material, wherein said first and second terminals and said first rail portion are formed on a first surface of the substrate, said layer of semiconductive material is formed over the first and second terminals and said first rail portion, the layer or other body of dielectric material is formed over the layer of semiconductive material, and said gate terminal and second rail portion are formed on a first surface of the layer or other body of dielectric material.

17. The circuit in accordance with claim 1 , further comprising a substrate and a layer of semiconductive material, wherein said first and second terminals and said first rail portion are formed on a first surface of the substrate, said layer of semiconductive material is formed at least between the first and second terminals to provide said channel, the layer or other body of dielectric material is formed over the layer of semiconductive material and the first and second terminals and the first rail portion, and said gate terminal and second rail portion are formed on a first surface of the layer or other body of dielectric material.

18. The circuit in accordance with claim 1 , further comprising a substrate and a layer of semiconductive material, wherein said gate terminal and said second rail portion are formed on a first surface of the substrate, the layer or other body of dielectric material of is formed over the gate terminal and said second rail portion, said first and second terminals and said first rail portion are formed over the layer or other body of dielectric material, and said layer of semiconductive material is formed at least between the first and second terminals to provide said channel.

19. The circuit in accordance with claim 1 , further comprising a substrate and a layer of semiconductive material, wherein said gate terminal and said second rail portion are formed on a first surface of the substrate, the layer or other body of dielectric material is formed over the gate terminal and said second rail portion, said layer of semiconductive material is formed over at least a portion of the layer or body of dielectric material covering the gate terminal, and said first and second terminals and said first rail portion are formed over the layer of semiconductive material and the layer or other body of dielectric material.

20. An electronic circuit comprising:
a first power rail;
a second power rail; and
a layer or other body of dielectric material,
wherein the first power rail comprises a first rail portion arranged on a first side of the layer or other body of dielectric material, and the second power rail comprises a second rail portion arranged on a second side of the layer or other body of dielectric material, said second side being opposite said first side, said first rail portion comprising a first grid or mesh of crossing and intersecting conductive elements and said second rail portion comprising a second grid or mesh of crossing and intersecting conductive elements, said first and second grids or meshes of crossing and intersecting conductive elements having substantially the same shape and being aligned with one another, on said opposite first and second sides, so as to form, together with a portion of the layer or other body of dielectric material sandwiched between them, a capacitor.

21. The electronic circuit in accordance with claim 20 , and further comprising a field effect transistor comprising:
a first terminal coupled directly or indirectly to the first power rail;
a second terminal coupled directly or indirectly

Assignees

• Pragmatic Printing Ltd

Inventors

• Cobb Brian

Classifications

• H10W20/496 Primary

  Capacitor integral with wiring layers · CPC title

• H10W20/427 Primary

  Power or ground buses · CPC title

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10W20/43

  Layouts of interconnections · CPC title