Semiconductor devices

Patent metadata

Field	Value
Publication number	US-11984507-B2
Application number	US-202117206229-A
Country	US
Kind code	B2
Filing date	Mar 19, 2021
Priority date	Aug 28, 2020
Publication date	May 14, 2024
Grant date	May 14, 2024

Abstract

A semiconductor device including an active region extending in a first direction on a substrate; channel layers vertically spaced apart on the active region; a gate structure extending in a second direction and intersecting the active region, the gate structure surrounding the channel layers; a source/drain region on the active region in contact with the channel layers; and a contact plug connected to the source/drain region, wherein the source/drain region includes a first epitaxial layer on side surfaces of the channel layers and including a first impurity; a second epitaxial layer on the first epitaxial layer and including the first impurity and a second impurity; and a third epitaxial layer on the second epitaxial layer and including the first impurity, and in a horizontal sectional view, the second epitaxial layer includes a peripheral portion having a thickness in the first direction that increases along the second direction.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an active region extending in a first direction on a substrate;
a plurality of channel layers vertically spaced apart from each other on the active region;
a gate structure extending in a second direction and intersecting the active region and the plurality of channel layers on the substrate, the gate structure surrounding the plurality of channel layers;
a source/drain region on the active region on at least one side of the gate structure and in contact with the plurality of channel layers; and
a contact plug connected to the source/drain region and extending in a vertical direction,
wherein:
the source/drain region includes a first epitaxial layer on side surfaces of the plurality of channel layers and including a first impurity; a second epitaxial layer on the first epitaxial layer and including the first impurity and a second impurity; and a third epitaxial layer on the second epitaxial layer and including the first impurity,
in a horizontal sectional view of a plane at a height level of one of the plurality of channel layers, the second epitaxial layer includes a peripheral portion having a thickness measured in the first direction that increases along the second direction,
a sum of thicknesses of the first epitaxial layer and the second epitaxial layer is about 2 nm to about 5 nm, and
the second epitaxial layer has a maximum thickness within a range from about 35% to less than 100% of the sum of the thicknesses of the first epitaxial layer and the second epitaxial layer.

2. The semiconductor device as claimed in claim 1 , wherein:
the first impurity includes boron (B), and
the second impurity includes carbon (C).

3. The semiconductor device as claimed in claim 2 , wherein:
the second epitaxial layer includes silicon-germanium, and
the second epitaxial layer includes carbon in a concentration of about 0.5 atomic % to about 4 atomic %.

4. The semiconductor device as claimed in claim 3 , wherein:
the first epitaxial layer includes silicon-germanium, and
a germanium concentration of the second epitaxial layer is greater than a germanium concentration of the first epitaxial layer.

5. The semiconductor device as claimed in claim 1 , wherein, in the horizontal sectional view, the second epitaxial layer includes:
a substantially flat first surface, and
a second surface that is a curved surface bent from the first surface and convex in a direction away from the gate structure.

6. The semiconductor device as claimed in claim 1 , wherein, in the horizontal sectional view, one surface of the second epitaxial layer, which is in contact with the third epitaxial layer, includes a portion that is concave inwardly toward the first epitaxial layer.

7. The semiconductor device as claimed in claim 1 , wherein, in the horizontal sectional view, one surface of the second epitaxial layer, which is in contact with the third epitaxial layer, is substantially flat.

8. The semiconductor device as claimed in claim 1 , wherein, in the horizontal sectional view, the first epitaxial layer includes:
a central portion having a first thickness, which is a maximum thickness of the first epitaxial layer as measured in the first direction, and
a peripheral portion whose thickness in the first direction decreases toward an end portion thereof along the second direction.

9. The semiconductor device as claimed in claim 1 , wherein, in the horizontal sectional view:
the second epitaxial layer includes a central portion having a first thickness in the first direction, and the thickness of the peripheral portion of the second epitaxial layer in the first direction is a second thickness, and
the second thickness is more than 1 to about 2 times the first thickness.

10. The semiconductor device as claimed in claim 1 , wherein an upper end of the second epitaxial layer is located at a higher height level than an upper end of the first epitaxial layer.

11. A semiconductor device, comprising:
an active region extending in a first direction on a substrate;
a plurality of channel layers vertically spaced apart from each other on the active region;
a gate structure extending in a second direction and intersecting the active region and the plurality of channel layers on the substrate, the gate structure surrounding the plurality of channel layers; and
a source/drain region on the active region on at least one side of the gate structure and in contact with the plurality of channel layers,
wherein:
the source/drain region includes a first epitaxial layer in contact with side surfaces of the plurality of channel layers and the active region and including silicon-germanium (SiGe) and boron (B); and
a second epitaxial layer on the first epitaxial layer and including silicon-germanium (SiGe), boron (B), and carbon (C),
the second epitaxial layer covers end portions of the first epitaxial layer in the second direction, and
in a horizontal sectional view at a plane passing through the source/drain region, the first epitaxial layer has a triangular shape or a quadrangular shape.

12. The semiconductor device as claimed in claim 11 , wherein the second epitaxial layer includes carbon in a concentration of about 0.5 atomic % to about 4 atomic %.

13. The semiconductor device as claimed in claim 11 , wherein, in the horizontal sectional view at the plane passing through the source/drain region:
the first epitaxial layer includes a first central portion having a first thickness in the first direction, and a first peripheral portion having a second thickness in the first direction, the second thickness being smaller than the first thickness, and
the second epitaxial layer includes a second central portion having a third thickness in the first direction, and a second peripheral portion having a fourth thickness in the first direction, the fourth thickness being greater than the third thickness.

14. The semiconductor device as claimed in claim 13 , wherein a sum of the second thickness and the fourth thickness is greater than a sum of the first thickness and the third thickness.

15. A semiconductor device, comprising:
an active region extending in a first direction on a substrate;
a gate structure extending in a second direction, perpendicular to the first direction, and intersecting the active region; and
a source/drain region on a recessed region of the active region at both sides of the gate structure, the source/drain region including a plurality of epitaxial layers,
wherein:
the plurality of epitaxial layers of the source/drain region include:
a first epitaxial layer covering an inner wall of the recessed region of the active region; and
a second epitaxial layer on the first epitaxial layer, in the recessed region of the active region,

the first epitaxial layer and the second epitaxial layer include silicon-germanium (SiGe) having different compositions,
each of the first epitaxial layer and the second epitaxial layer includes a first impurity including boron (B),
the second epitaxial layer further includes a second impurity including carbon (C),
at least one of the first epitaxial layer and the second epitaxial layer includes different portions having different thicknesses in the first direction, and
in a horizontal sectional view along a plane passing through the source/drain region:
the first epitaxial layer includes a central portion having a first thickness, that is a maximum thickness in the first direction, and a peripheral portion having a thickness in the first direction that decreases toward an end thereof along the second direction, and
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Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Dongwoo
• Kim Jinbum
• Kim Gyeom
• Kim Dohee
• Lee Seunghun

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D62/151 Primary

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title