Layout of integrated circuit

Patent metadata

Field	Value
Publication number	US-11984442-B2
Application number	US-202217715974-A
Country	US
Kind code	B2
Filing date	Apr 8, 2022
Priority date	Sep 28, 2021
Publication date	May 14, 2024
Grant date	May 14, 2024

Abstract

A layout includes a first and a second standard cells abutting along a boundary line. The first cell includes first fins. An edge of the first fins closest to and away from the boundary line by a distance D 1 . A first gate line over-crossing the first fins protrudes from the edge by a length L 1 . The second cell includes second fins. An edge of the second fins closest to and away from the boundary line by a distance D 2 . A second gate line over-crossing the second fins protrudes from the edge by a length L 2 . Two first dummy gate lines at two sides of the first fins and two second dummy lines at two sides of the second fins are respectively away from the boundary line by a distance S. The lengths L 1 and L 2 , the distances S, D 1 and D 2 have the relationships: L 1 ≤D 1 −S, L 2 ≤D 2 −S, and D 1 ≠D 2.

First claim

What is claimed is:

1. An integrated circuit layout, comprising:
a first row of standard cells and a second row of standard cells abutting along a boundary line extending along a first direction;
a first standard cell of the first row of standard cells, comprising:
a plurality of first fin structures, respectively extending along the first direction and arranged in parallel along a second direction that is perpendicular to the first direction;
a first gate line extending along the second direction to stride across the first fin structures, wherein a line end of the first gate line protrudes from an edge of one of the plurality of first fin structures that is most adjacent to the boundary line by a length L 1 ; and
two first dummy gate lines, disposed at two sides of the plurality of first fin structures and respectively extending along the second direction; and

a second standard cell of the second row of standard cells, comprising:
a plurality of second fin structures, respectively extending along the first direction and arranged in parallel along the second direction;
a second gate line extending along the second direction to stride across the plurality of second fin structures, wherein a line end of the second gate line protrudes from an edge of one of the plurality of second fin structures that is most adjacent to the boundary line by a length L 2 ; and
two second dummy gate lines, disposed at two sides of the second fin structures and respectively extending along the second direction,
wherein the two first dummy gate lines and the two second dummy gate lines are respectively away from the boundary line by a distance S, the edge of the one of the plurality of first fin structures is away from the boundary line by a distance D 1 , the edge of the one of the plurality of second fin structures is away from the boundary line by a distance D 2 , and the length L 1 , the length L 2 , the distance S, the distance D 1 and the distance D 2 comprise the relationships:
L 1 ≤D 1 −S;
L 2 ≤D 2 −S ; and
D 1≠ D 2.

2. The integrated circuit layout according to claim 1 , wherein the first standard cell and the second standard cell have a same cell height along the second direction.

3. The integrated circuit layout according to claim 1 , wherein the length L 2 is equal to or larger than the length L 1 .

4. The integrated circuit layout according to claim 1 , wherein the two first dummy gate lines and the two second dummy gate lines comprise a same dummy gate line length along the second direction.

5. The integrated circuit layout according to claim 1 , wherein a gate line length of the first gate line along the second direction and a dummy gate line length of the two first dummy gate lines along the second direction are the same.

6. The integrated circuit layout according to claim 1 , wherein a gate line length of the second gate line along the second direction is smaller than a dummy gate line length of the two second dummy gate lines along the second direction.

7. The integrated circuit layout according to claim 1 , wherein the first gate line is away from the boundary line by a distance S 1 , and the second gate line is away from the boundary line by a distance S 2 , wherein the distance S 1 and the distance S 2 are equal to or larger than the distance S, respectively.

8. The integrated circuit layout according to claim 1 , wherein the first standard cell comprises a plurality of the first gate lines arranged in parallel along the first direction and striding across the first fin structures, and the second standard cell comprises a plurality of the second gate lines arranged in parallel along the first direction and striding across the second fin structures, wherein at least a portion of the first gate lines are aligned to at least a portion of the second gate lines along the second direction.

9. The integrated circuit layout according to claim 8 , wherein line ends of the first gate lines are aligned with each other along the first direction.

10. The integrated circuit layout according to claim 1 , wherein the two first dummy gate lines are aligned to the two second dummy gate lines along the second direction.

11. The integrated circuit layout according to claim 1 , wherein a number of the plurality of first fin structures and a number of the plurality of second fin structures are different.

12. The integrated circuit layout according to claim 1 , wherein the plurality of first fin structures comprise a first conductivity type, the plurality of second fin structures comprise a second conductivity type, the first conductivity type and the second conductivity type are opposite.

13. The integrated circuit layout according to claim 1 , wherein line ends of the plurality of first fin structures are flush along the second direction and covered by the two first dummy gate lines, line ends of the plurality of second fin structures are flush along the second direction and covered by the two second dummy gate lines.

Assignees

• United Microelectronics Corp

Inventors

• Chen Ruei-Yau
• Wang Wei-Jen
• Wu Kun-Yuan
• Chen Chien-Fu
• Hsu Chen-Hsien

Classifications

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/83138

  the IGFETs characterised by having different shapes or dimensions of their gate conductors · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10D84/907

  CMOS gate arrays · CPC title