Reconfigurable digital signal processing (DSP) vector engine

Patent metadata

Field	Value
Publication number	US-11983530-B2
Application number	US-202016833164-A
Country	US
Kind code	B2
Filing date	Mar 27, 2020
Priority date	Mar 27, 2020
Publication date	May 14, 2024
Grant date	May 14, 2024

Abstract

Systems and methods described herein may relate to providing a dynamically configurable circuitry able to process data associated with a variety of matrix dimensions using one or more complex number operations, one or more real number operations, or both. Configurations may be applied to the configurable circuitry to program the configurable circuitry for a next operation. The configurable circuitry may process data according to a variety of operations based at least in part on operation of a repeated processing element coupled in a compute network of processing elements.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a first circuit;
interface circuitry; and
an integrated accumulator coupled to the first circuit through the interface circuitry, wherein the integrated accumulator is configurable to perform a complex number operation at a first time and to perform a real number operation at a second time, wherein the integrated accumulator performs the real number operation using first real type data as an input and generates second real type data as an output, wherein the integrated accumulator comprises a plurality of multipliers and a plurality of adders, wherein the integrated accumulator has a reprogrammable data width, and wherein a data width of data processed using the complex number operation or the real number operation is different from a data width of the interface circuitry.

2. The integrated circuit of claim 1 , wherein a first portion of the processing circuit comprises a first compute network comprising a first subset of the plurality of multipliers and the plurality of adders arranged in a first pattern, and wherein a second portion of the processing circuit comprises a second compute network comprising a second subset of the plurality of multipliers and the plurality of adders also arranged in the first pattern.

3. The integrated circuit of claim 1 , wherein the data width of data processed using the complex number operation or the real number operation is different from a data width of the first circuit.

4. The integrated circuit of claim 1 , wherein the integrated accumulator comprises multiplexing circuitry configured to route data through a multiplier of the plurality of multipliers to perform the complex number operation on the data.

5. The integrated circuit of claim 1 , wherein the integrated accumulator comprises multiplexing circuitry configured to route data through a multiplier of the plurality of multipliers to perform the real number operation on the data.

6. The integrated circuit of claim 1 , wherein the integrated accumulator is configured to perform the complex number operation and to perform a different complex number operation in parallel.

7. The integrated circuit of claim 1 , wherein the integrated accumulator is configured to perform the complex number operation at a first time and to perform a Radix-2 number operation at a second time using a same circuit.

8. The integrated circuit of claim 1 , wherein the integrated accumulator is configured to perform the complex number operation on a first matrix of a first size at a first time and to perform the complex number operation of a second matrix of a second size different from the first size at a second time without reconfiguring between the first time and the second time.

9. The integrated circuit of claim 1 , wherein the integrated accumulator is configured to perform the complex number operation on a first matrix at a first time, wherein the integrated accumulator is configured to perform the real number operation on a second matrix at the first time, wherein the integrated accumulator is configured to perform the complex number operation on a third matrix at a second time, wherein the integrated accumulator is configured to perform the real number operation on a fourth matrix at the second time, wherein the third matrix is larger than the first matrix, and wherein the fourth matrix is smaller than the second matrix.

10. The integrated circuit of claim 1 , comprising a controller configured to operate the integrated accumulator, wherein the integrated accumulator comprises an instruction decoder configured to generate and apply a configuration for the integrated accumulator in response to an instruction generated by the controller to operate the integrated accumulator.

11. The integrated circuit of claim 1 , wherein the integrated accumulator comprises a compute network coupled to an instruction decoder, wherein the compute network comprises one or more multipliers of the plurality of multipliers and one or more adders of the plurality of adders and is configured with control signals generated by the instruction decoder to adjust a relative weighting associated with the one or more multipliers or the one or more adders.

12. A method of operating a compute network of a first processing circuit to perform a complex number operation, comprising:
receiving, via the first processing circuit, an instruction from a controller;
receiving, via the first processing circuit, input data;
generating, via the first processing circuit, a configuration for the compute network in response to the instruction;
programming, via the first processing circuit, an integrated accumulator of the compute network based on the configuration, wherein the integrated accumulator is configurable to perform the complex number operation at a first time and to perform a real number operation at a second time based on the configuration, wherein the real number operation is performed on first real type data as an input and generates second real type data as an output, wherein the integrated accumulator is configurable to perform the complex number operation on a first matrix of a first size at a first time and to perform the complex number operation of a second matrix of a second size different from the first size at a second time without reconfiguring between the first time and the second time;
transmitting, via the first processing circuit, the input data through the first processing circuit to perform the complex number operation on the input data; and
outputting, via the first processing circuit, the input data to a first circuit of an integrated circuit.

13. The method of claim 12 , further comprising applying the configuration to the compute network by:
generating, via the first processing circuit, an operational mask; and
applying, via the first processing circuit, the operational mask to the compute network to deactivate a subset of inputs of the compute network from applying the input data to the complex number operation.

14. The method of claim 12 , further comprising applying the configuration to the compute network by:
configuring, via the first processing circuit, multiplexing circuitry of the compute network, wherein the multiplexing circuitry is configured to route the input data through the compute network to perform the complex number operation on the input data after application of the configuration.

15. The method of claim 12 , wherein the integrated accumulator has a reprogrammable data width, and wherein a data width of data processed using the complex number operation or the real number operation is different from a data width of the interface circuitry.

16. A system, comprising:
a first circuit; and
an integrated accumulator coupled to the first circuit, wherein the integrated accumulator is configurable to perform one or more real number operations and one or more complex number operations, wherein the real number operation is performed on real type data as an input and generates real type data as an output, wherein the integrated accumulator comprises a compute network coupled to an instruction decoder, wherein the compute network comprises one or more multipliers and one or more adders and is configured with control signals generated by the instruction decoder to adjust a relative weighting associated with the one or more multipliers or the one or more adders, wherein the integrated accumulator is configurable to:
receive an instruction from a controller;
receive input data from the first circuit;
generate a configuration for the compute network in response to the instruc

Assignees

• Intel Corp

Inventors

• Nagi Sumeet Singh
• Sheikh Farhana
• Weber Scott Jeremy
• Rathore Uneeb Yaqub

Classifications

• G06F9/3001 Primary

  Arithmetic instructions · CPC title

• G06F7/4806

  Computations with complex numbers · CPC title

• G06F7/49

  Computations with a radix, other than binary, 8, 16 or decimal, e.g. ternary, negative or imaginary radices, mixed radix {non-linear PCM (G06F7/4824 takes precedence)} · CPC title

• G06F7/50

  Adding; Subtracting (G06F7/483 - G06F7/491, G06F7/544 - G06F7/556 take precedence) · CPC title

• G06F7/523

  Multiplying only · CPC title