Semiconductor devices and methods for forming the same

Patent metadata

Field	Value
Publication number	US-11980096-B2
Application number	US-202016999966-A
Country	US
Kind code	B2
Filing date	Aug 21, 2020
Priority date	Nov 6, 2019
Publication date	May 7, 2024
Grant date	May 7, 2024

Abstract

A semiconductor device includes a substrate. The semiconductor device also includes a semiconductor layer disposed in the substrate. The semiconductor device further includes a first dielectric layer disposed on the semiconductor layer. The semiconductor device includes a second dielectric layer disposed on the first dielectric layer. The semiconductor device also includes a pair of thermopile segments disposed on the second dielectric layer. The first dielectric layer and the second dielectric layer form a chamber.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate comprising a semiconductor material;
a semiconductor layer disposed in the semiconductor material of the substrate;
a first dielectric layer disposed on the semiconductor layer, wherein the semiconductor layer and the first dielectric layer are used as a reflecting layer of the semiconductor device;
a second dielectric layer disposed on the first dielectric layer; and
a pair of thermopile segments disposed on the second dielectric layer;
wherein the first dielectric layer and the second dielectric layer form a chamber in the semiconductor material of the substrate, the first dielectric layer is conformally formed on a bottom and a sidewall of the chamber, and the first dielectric layer in the chamber extends beyond the semiconductor layer in a direction parallel to a bottom surface of the substrate.

2. The semiconductor device as claimed in claim 1 , wherein the semiconductor layer is a heavily doped N-type semiconductor layer or a heavily doped P-type semiconductor layer.

3. The semiconductor device claimed in claim 2 , wherein a concentration of the semiconductor layer is greater than 1E16cm −3 .

4. The semiconductor device as claimed in claim 1 , wherein a material of the pair of thermopile segments comprises an N-type semiconductor and a P-type semiconductor.

5. The semiconductor device as claimed in claim 1 , further comprising:
a semiconductor element disposed in the substrate and adjacent to the pair of thermopile segments and the chamber.

6. The semiconductor device as claimed in claim 5 , wherein the semiconductor element is separated from the pair of thermopile segments and the chamber by the first dielectric layer and the second dielectric layer.

7. A semiconductor device, comprising:
a substrate comprising a semiconductor material having a chamber in the semiconductor material of the substrate;
a dielectric layer surrounding the chamber;
a semiconductor layer disposed at a bottom of the dielectric layer; and
a pair of thermopile segments disposed on the dielectric layer,
wherein the dielectric layer has a first portion conformally formed on a bottom and a sidewall of the chamber and a second portion conformally formed on a top of the chamber, the first portion of the dielectric layer in the chamber extends beyond the semiconductor layer in a direction parallel to a bottom surface of the substrate, and the semiconductor layer and the first portion of the dielectric layer are used as a reflecting layer of the semiconductor device.

8. The semiconductor device as claimed in claim 7 , wherein the dielectric layer comprises:
a first dielectric layer disposed at sidewalls and a bottom of the chamber; and
a second dielectric layer disposed at a top of the chamber.

9. The semiconductor device as claimed in claim 7 , wherein the semiconductor layer is a heavily doped N-type semiconductor layer or a heavily doped P-type semiconductor layer.

10. The semiconductor device as claimed in claim 9 , wherein a concentration of the semiconductor layer is greater than 1E16cm −3 .

11. The semiconductor device as claimed in claim 7 , wherein a material of the pair of thermopile segments comprises an N-type semiconductor and a P-type semiconductor.

12. The semiconductor device as claimed in claim 1 , wherein a spacing between the outermost side of the semiconductor layer and the outermost side of the first dielectric layer in the chamber is greater than 5 μm.

Assignees

• Nuvoton Technology Corp

Inventors

• Chiu In-Shiang
• Chen Kuang-Chu
• Hsiao Peng-Chan
• Liu han-ying

Classifications

• H10N10/17 Primary

  characterised by the structure or configuration of the cell or thermocouple forming the device · CPC title

• H10N10/01 Primary

  Manufacture or treatment · CPC title

• G01K7/028

  using microstructures, e.g. made of silicon · CPC title

• H10N10/851

  comprising inorganic compositions · CPC title