Time encoded data communication protocol, apparatus and method for generating and receiving a data signal

Patent metadata

Field	Value
Publication number	US-11979177-B2
Application number	US-202217810845-A
Country	US
Kind code	B2
Filing date	Jul 6, 2022
Priority date	Sep 18, 2017
Publication date	May 7, 2024
Grant date	May 7, 2024

Abstract

An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

First claim

What is claimed is:

1. A method for processing a data signal, the method comprising:
receiving a first group of at least one payload data symbol;
sending a negative acknowledge signal if the received first group contains an error;
receiving a second group of at least one payload data symbol:
at a number of groups of payload data symbols after sending the negative acknowledge signal, or
receiving the second group at a number of groups of payload data symbols after
receiving the first group.

2. The method of claim 1 further comprising:
demodulating the payload data symbols of the first group using a first demodulation scheme; and
demodulating the payload data symbols of the second group using a second demodulation scheme.

3. The method of claim 2 , wherein the second demodulation scheme is more robust than the first demodulation scheme.

4. The method of claim 3 , wherein a symbol separation time of the second demodulation scheme is longer than the symbol separation time of the first demodulation scheme.

5. The method of claim 1 , further comprising:
receiving the first group and the second group via a first transmission link; and
transmitting the negative acknowledge signal via a second transmission link.

6. A method for generating a data signal, the method comprising:
transmitting a first group of at least one payload data symbol; and
upon receiving a negative acknowledge signal, transmitting a second group of at least one payload data symbol related to the first group:
at a number of groups of payload data symbols after transmitting the first group, or
at a number of groups of payload data symbols after receiving the negative acknowledge signal.

7. The method of claim 6 , further comprising:
modulating payload data into the first group using a first modulation scheme; and
modulating the payload data into the second group using a second modulation scheme.

8. The method of claim 7 , wherein the second modulation scheme is more robust than the first modulation scheme.

9. The method of claim 8 , wherein a symbol separation time of the second modulation scheme is longer than the symbol separation time of the first modulation scheme.

10. The method of claim 6 , further comprising:
transmitting the first group and the second group via a first transmission link; and
receiving the negative acknowledge signal via a second transmission link.

11. An apparatus for processing a data signal, the apparatus comprising:
a receiver circuit configured to receive groups of payload data symbols;
an error detection circuit configured to generate a negative acknowledge signal if a first group of at least one payload data symbol contains an error; and
error correction circuitry configured to use a second group of at least one payload data symbol to replace the first group, the second group being received:
at a number of groups of payload data symbols after sending the negative acknowledge signal or
at a number of groups of payload data symbols after receiving the first group.

12. The apparatus of claim 11 , further comprising:
demodulation circuitry configured to demodulate the payload data symbols of the first group using a first demodulation scheme and to demodulate the payload data symbols of the second group using a second demodulation scheme.

13. The apparatus of claim 11 , further comprising an input interface for a first transmission link coupled to the receiver circuit to receive a data signal comprising the groups of payload data symbols.

14. The apparatus of claim 13 , wherein the input interface is configured to receive the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period, and the second signal edge and the third signal edge being separated by a second time period; the first time period being based on a first payload data symbol, and the second time period being based on a second payload data symbol.

15. The apparatus of claim 13 , further comprising an output interface for transmitting the negative acknowledge signal via a second transmission link, the output interface coupled to the error detection circuit.

16. An apparatus for generating a data signal, the apparatus comprising:
a transmitter circuit configured to transmit a first group of at least one payload data symbol; and
an input interface configured to receive a negative acknowledge signal, wherein
the transmitter circuit is further configured to transmit a second group of at least one payload data symbol related to the first group:
at a number of groups of payload data symbols after transmitting the first group, or
at a number of groups of payload data symbols after receiving the negative acknowledge signal.

17. The apparatus of claim 16 , wherein the transmitter circuit further comprises a modulator circuit configured to modulate payload data into the first group using a first modulation scheme; and to modulate the payload data into the second group using a second modulation scheme.

18. The apparatus of claim 17 , wherein a symbol separation time of the second modulation scheme is longer than the symbol separation time of the first modulation scheme.

19. The apparatus of claim 16 , further comprising:
an output interface configured to output a data signal comprising the first group and the second group; and
an input interface configured to receive the negative acknowledge signal via a second transmission link.

20. The apparatus of claim 19 , wherein the output interface is configure to output the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period, and the second signal edge and the third signal edge being separated by a second time period; the first time period being based on a first payload data symbol, and the second time period being based on a second payload data symbol.

21. A physical layer controller for a communication interface, the physical layer controller comprising an apparatus for processing a data signal, the apparatus for processing a data signal comprising:
a receiver circuit configured to receive a first group of at least one payload data symbol;
an error detection circuit configured to send a negative acknowledge signal if the first group contains an error; and
error correction circuitry configured to use a second group of at least one payload data symbol to replace the first group, the second group being received:
at a number of groups of payload data symbols after sending the negative acknowledge signal, or
at a number of groups of payload data symbols after receiving the first group.

Assignees

• Intel Corp

Inventors

• Banin Elan
• Mann Eytan
• Banin Rotem
• Gernizky Ronen
• Degani Ofir
• Kushnir Igal
• Porat Shahar
• Rubin Amir
• Volokitin Vladimir
• Kashani Elinor
• Felsenstein Dmitry
• Eshkoli Ayal
• Davidson Tal
• Ooi Eng Hun
• Tsfati Yossi
• Shimon Ran

Classifications

• H04B1/04 Primary

  Circuits · CPC title

• H04L7/0331

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title