Level shifter

Patent metadata

Field	Value
Publication number	US-11979156-B2
Application number	US-202318187262-A
Country	US
Kind code	B2
Filing date	Mar 21, 2023
Priority date	May 12, 2021
Publication date	May 7, 2024
Grant date	May 7, 2024

Abstract

A level shifter includes a buffer circuit, a first shift circuit, and a second shift circuit. The buffer circuit provides a first signal and a first inverted signal to the first shift circuit, such that the first shift circuit provides a second signal and a second inverted signal to the second shift circuit. The second shift circuit generates a plurality of output signals according to the second signal and the second inverted signal. The first shift circuit includes a plurality of first stacking transistors and a first voltage divider circuit. The first voltage divider circuit is electrically coupled between a first system high voltage terminal and a system low voltage terminal. The first voltage divider circuit is configured to provide a first inner bias to gate terminals of the first stacking transistors.

First claim

What is claimed is:

1. A level shifter comprising:
a buffer circuit providing a first signal and a first inverted signal of opposite phases;
a first shift circuit electrically coupled between a first system high voltage terminal and a system low voltage terminal, and the first shift circuit being configured to provide a second signal and a second inverted signal of the opposite phases according to the first signal and the first inverted signal; and
a second shift circuit electrically coupled between a second system high voltage terminal and the system low voltage terminal, wherein the second shift circuit generates a plurality of output signals according to the second signal and the second inverted signal,
wherein the first signal and the first inverted signal operate in a positive voltage domain, and wherein the second signal and the second inverted signal operate in a negative voltage domain.

2. The level shifter of claim 1 , wherein the first shift circuit comprises:
a plurality of first stacking transistors; and
a first voltage divider circuit, electrically coupled between the first system high voltage terminal and the system low voltage terminal, and being configured to provide a first inner bias to gate terminals of the first stacking transistors.

3. The level shifter of claim 2 , wherein the first shift circuit further comprises:
two pull-up transistors electrically coupled to the first system high voltage terminal, the two pull-up transistors being enabled respectively according to the first signal and the first inverted signal;
two first cross-coupled transistors electrically coupled to the system low voltage terminal, the two first cross-coupled transistors being enabled respectively according to the second signal and the second inverted signal; and
a plurality of first stacking transistors, electrically coupled between the two pull-up transistors and the two first cross-coupled transistors.

4. The level shifter of claim 3 , wherein each of the two first cross-coupled transistors is implemented by an N-type metal oxide semiconductor with a deep N-well, wherein the deep N-well of each of the two first cross-coupled transistors is electrically coupled to the second system high voltage terminal, wherein a base terminal and a source terminal of each of the two first cross-coupled transistors are electrically coupled.

5. The level shifter of claim 3 , wherein the first voltage divider circuit comprises:
two first voltage divider transistors electrically coupled between the first system high voltage terminal and the system low voltage terminal, the two first voltage divider transistors being configured to provide the first inner bias to the gate terminals of the first stacking transistors.

6. The level shifter of claim 1 , wherein the second shift circuit comprises:
a second voltage divider circuit electrically coupled between the second system high voltage terminal and a ground terminal, and being configured to provide a plurality of second inner biases.

7. The level shifter of claim 6 , wherein a voltage of the system low voltage terminal is lower than a voltage of the ground terminal.

8. The level shifter of claim 6 , wherein the second shift circuit further comprises:
two second cross-coupled transistors electrically coupled between the second system high voltage terminal and two first output terminals;
a plurality of second stacking transistors electrically coupled between the two first output terminals and two second output terminals, the second stacking transistors being configured to respectively receive one part of the second inner biases;
a plurality of third stacking transistors electrically coupled between the two second output terminals and two third output terminals, the third stacking transistors being configured to respectively receive another part of the second inner biases; and
two pull-down transistors electrically coupled between the two third output terminals and the system low voltage terminal, the two pull-down transistors being enabled according to the second signal and the second inverted signal, wherein the two first output terminals, the two second output terminals, and the two third output terminals are configured to output the output signals.

9. The level shifter of claim 8 , wherein the second voltage divider circuit comprises:
a plurality of second voltage divider transistors electrically coupled between the second system high voltage terminal and a node, the second voltage divider transistors being configured to provide the part of the second inner biases to gate terminals of the second stacking transistors; and
a plurality of third voltage divider transistors electrically coupled between the node and the ground terminal, the third voltage divider transistors being configured to provide the another part of the second inner biases to gate terminals of the third stacking transistors.

10. The level shifter of claim 1 , wherein a voltage of the second system high voltage terminal is higher than a voltage of the first system high voltage terminal.

Assignees

• Au Optronics Corp

Inventors

• Lu Yi-Chen
• Li Hsu-Chi
• Chen Yi-Jan
• Jaw Boy-Yiing
• Chuang Chin-Tang
• Chen Chung-Hung

Classifications

• H03K3/356113 Primary

  using additional transistors in the input circuit · CPC title

• H03K17/102

  in field-effect transistor switches · CPC title

• H03K19/018521

  of complementary type, e.g. CMOS · CPC title

• H03K19/018507 Primary

  Interface arrangements · CPC title

• H03K3/356182 Primary

  with additional means for controlling the main nodes · CPC title