Differential analog multiplier-accumulator

Patent metadata

Field	Value
Publication number	US-11977936-B2
Application number	US-202017139945-A
Country	US
Kind code	B2
Filing date	Dec 31, 2020
Priority date	Dec 31, 2020
Publication date	May 7, 2024
Grant date	May 7, 2024

Abstract

A differential multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to respective positive and negative unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. Each positive and negative unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each positive and negative unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors and to an analog to digital converter to generate a digital output product. The charge transfer lines may span multiple unit elements.

First claim

We claim:

1. A differential multiplier-accumulator operative to multiply an A digital input having a number of bits with a B digital input having a number of bits, the differential multiplier-accumulator comprising:
a positive value unit element part;
a negative value unit element part;
a differential analog to digital converter (ADC) having a positive input coupled to an output of the positive value unit element part and a negative input coupled to an output of the negative value unit element part, the ADC forming an output;
the positive value unit element part comprising:
a plurality of AND-groups equal in number to the number of bits of the A digital input, each AND-group further comprising a plurality of AND gates equal in number to the number of bits of the A digital input, each AND gate of each AND-group receiving a unique one of the bits of the A digital input and one of the bits of the B digital input, the AND gate of each AND-group coupled to a particular charge transfer line through a charge transfer capacitor having a value C;
a charge summing unit comprising a plurality of charge summing capacitors, each charge summing capacitor having a first terminal coupled to a particular one of the charge transfer lines, each charge summing capacitor having a second terminal coupled to the positive input of the ADC;

the negative value unit element part comprising:
a plurality of AND-groups equal in number to the number of bits of the A digital input, each AND-group further comprising a plurality of AND gates equal in number to the number of bits of the A digital input, each AND gate of each AND-group receiving a unique one of the bits of the A digital input and one of the bits of the B digital input;
a charge summing unit comprising a plurality of charge summing capacitors, each charge summing capacitor having a first terminal coupled to a particular one of the charge transfer lines, each charge summing capacitor having a second terminal coupled to the negative input of the ADC.

2. The differential multiplier-accumulator of claim 1 where an analog charge line weight number for each of the charge transfer lines is determined by a sum of a bit number of the A digital input and a bit number of the B digital input associated with a particular AND gate, an analog charge line weight being a power of two to the analog charge line weight number for a respective charge transfer line.

3. The differential multiplier-accumulator of claim 2 where the charge transfer capacitors coupled to the AND gate have the same value and the analog charge line weight, the analog charge line weight determined by a size of a charge line capacitor associated with an analog charge line.

4. The differential multiplier-accumulator of claim 2 where analog charge lines with the same analog charge line weight number, wherein each analog charge line is a single analog charge line.

5. The differential multiplier-accumulator of claim 2 where analog charge lines with the same analog charge line weight number are separate analog charge lines.

6. The differential multiplier-accumulator of claim 1 where the A digital input or the B digital input has three bits or four bits.

7. The differential multiplier-accumulator of claim 1 where a sum of capacitances of charge transfer capacitors, corresponding to the positive and negative value unit element parts, coupled to a particular analog charge line has a value which is at least eight times greater than a value of an associated charge summing capacitor coupled to the particular analog charge line.

8. The differential multiplier-accumulator of claim 1 where each charge summing capacitor of the positive and negative value unit element parts has a value Cs*2 n where n is a weighting bit order of an associated analog charge line and for each positive and negative unit element part, the total capacitance of charge transfer capacitors coupled to a particular analog charge line is at least eight times larger than Cs.

9. A differential unit element (UE) for multiplying an A digital value having a number of bits and a B digital value having a number of bits and transferring a result to an analog charge bus, the differential unit element comprising:
a positive analog charge bus comprising a plurality of positive analog charge lines, the positive analog charge lines coupled to a positive charge summing unit having a positive output;
a negative analog charge bus comprising a plurality of negative analog charge lines, the negative analog charge lines coupled to a negative charge summing unit having a negative output;
an analog to digital converter (ADC) having a positive input coupled to the positive output and a negative input coupled to the negative output, the ADC generating an output equal to the negative input subtracted from the positive input;
a positive unit element part and a negative unit element part;
the positive unit element part comprising a plurality of AND-groups, each AND-group further comprising a plurality of AND gates having one input coupled to a unique one of the bits of the A digital value and an input coupled to one of the bits of the B digital value, each AND gate coupled through a charge transfer capacitor to a positive analog charge line;
the negative unit element part comprising a plurality of AND-groups, each AND-group further comprising a plurality of AND gates having one input coupled to a unique one of the bits of the A digital value and an input coupled to one of the bits of the B digital value, each AND gate coupled through a charge transfer capacitor to a negative analog charge line;
the positive analog charge lines and negative analog charge lines being coupled to a binary weighted positive charge summing unit and a binary weighted negative charge summing unit, respectively, each of the binary weighted positive charge summing unit and the binary weighted negative charge summing unit comprising a plurality of binary weighted capacitors according to a bit order of the analog charge line such that a charge transfer from each increased bit number of the sum of a bit number of the A digital value and a bit number of the B digital value is a factor of two greater than a charge transfer from a respective positive or negative analog charge line with a respective bit number lower by one.

10. The differential UE of claim 9 where each binary weighted charge summing capacitor associated with a charge transfer line with bit order n has an associated capacitance value Cs*2 n .

11. The differential UE of claim 10 where a capacitance equal to the sum of charge transfer capacitors coupled to a charge transfer line is at least eight times greater than a capacitance of an associated charge summing capacitor.

12. The differential UE of claim 9 where the negative and positive analog charge lines include capacitors for introducing a bias charge.

13. The differential UE of claim 9 where the negative and positive analog charge lines include switches for discharging analog transfer capacitors and charge summing capacitors.

Assignees

• Ceremorphic Inc

Inventors

• Kraemer Martin
• Boesch Ryan
• Xiong Wei

Classifications

• G06G7/16 Primary

  for multiplication or division {(G06G7/19 and G06G7/24 take precedence; measuring electric power G01R21/00)} · CPC title

• G06F7/5443 Primary

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06F2207/4824

  Neural networks · CPC title