Tiling display apparatus

Patent metadata

Field	Value
Publication number	US-11977807-B2
Application number	US-202217979607-A
Country	US
Kind code	B2
Filing date	Nov 2, 2022
Priority date	Dec 31, 2021
Publication date	May 7, 2024
Grant date	May 7, 2024

Abstract

A tiling display apparatus includes a plurality of display modules connected to one another through a first interface circuit and a second interface circuit and a set board receiving a defect occurrence and position signal, generated in a broken-down module of the plurality of display modules, from the broken module through the first interface circuit in a first period, generating a defect recognition completion signal in a second period succeeding the first period, and transferring the defect recognition completion signal to the broken-down module through the second interface circuit in the second period.

First claim

What is claimed is:

1. A tiling display apparatus comprising:
a plurality of display modules connected to one another through a first interface circuit and a second interface circuit, each of the plurality of display modules connected to the first interface circuit and the second interface circuit; and
a set board receiving a defect occurrence and position signal, generated in a broken-down module of the plurality of display modules, from the broken-down module through the first interface circuit but not the second interface circuit in a first period, generating a defect recognition completion signal that is indicative of the reception of the defect occurrence and position signal from the broken-down module via the first interface circuit in a second period succeeding the first period, and transferring the defect recognition completion signal to the broken-down module through the second interface circuit but not the first interface circuit in the second period.

2. The tiling display apparatus of claim 1 , wherein each of the defect occurrence and position signal and the defect recognition completion signal is a pulse signal which swings between a high logic voltage and a low logic voltage,
the defect occurrence and position signal comprises a first falling edge and one or more first rising edges arranged next to the first falling edge, and
the defect recognition completion signal comprises a second rising edge.

3. The tiling display apparatus of claim 2 , wherein, in the first period, the set board recognizes occurrence of a defect of the broken-down module on the basis of the first falling edge of the defect occurrence and position signal, counts the first rising edge of the defect occurrence and position signal, and recognizes a position of the broken-down module on the basis of a number of first rising edges, and
in the second period, the broken-down module recognizes a defect recognition completion state of the set board on the basis of the second rising edge of the defect recognition completion signal.

4. The tiling display apparatus of claim 2 , wherein a number of first rising edges varies based on a connection position of the broken-down module of the plurality of display modules.

5. The tiling display apparatus of claim 2 , wherein a number of first rising edges corresponds to a connection sequence, based on the second interface circuit, of the broken-down module of the plurality of display modules.

6. The tiling display apparatus of claim 1 , wherein the set board further receives a defect history signal of the broken-down module from the broken-down module through the first interface circuit in a third period succeeding the second period.

7. The tiling display apparatus of claim 6 , wherein the defect history signal is a pulse signal which swings between a high logic voltage and a low logic voltage, and
the defect history signal comprises one or more third rising edges.

8. The tiling display apparatus of claim 7 , wherein the set board counts the third rising edges of the defect history signal and recognizes, as a defect history of the broken-down module, one piece of defect candidate information of a breakdown diagnosis list on the basis of a number of third rising edges.

9. The tiling display apparatus of claim 8 , wherein the breakdown diagnosis list of the broken-down module comprises pieces of defect candidate information having different setting sequences, and
the number of third rising edges corresponds to a setting sequence, of the piece of defect candidate information corresponding to a defect history of the broken-down module, among the pieces of the defect candidate information.

10. The tiling display apparatus of claim 1 , wherein each of the first interface circuit and the second interface circuit is implemented with a serial peripheral interface.

11. A tiling display apparatus comprising:
a set board; and
a plurality of display modules connected to one another through a first interface circuit and a second interface circuit, each of the plurality of display modules connected to the first interface circuit and the second interface circuit,
wherein each of the plurality of display modules comprises
a timing controller configured to: generate, when the display module is broken-down, a defect occurrence and position signal, and transfer the defect occurrence and position signal to the set board through the first interface circuit but not the second interface circuit in a first period, and receive a defect recognition completion signal, which is generated by the set board, through the second interface circuit but not the first interface circuit in a second period succeeding the first period,
wherein the defect recognition completion signal is indicative that the set board received the defect occurrence and position signal from the broken-down module via the first interface circuit.

12. The tiling display apparatus of claim 11 , wherein the timing controller further generates a defect history signal of the display module and transfers the defect history signal to the set board through the first interface circuit in a third period succeeding the second period.

Assignees

• Lg Display Co Ltd

Inventors

• Park Sang Woo
• Kim Tae Gung

Classifications

• G06F3/1446 Primary

  display composed of modules, e.g. video walls · CPC title

• G06F11/162

  Displays · CPC title

• G09G3/006 Primary

  Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

• G06F2201/86

  Event-based monitoring · CPC title

• G09G2300/026

  Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions · CPC title