Telematics device with input/output expansion power fault handling

US11977427B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11977427-B2
Application numberUS-202217893440-A
CountryUS
Kind codeB2
Filing dateAug 23, 2022
Priority dateAug 25, 2021
Publication dateMay 7, 2024
Grant dateMay 7, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for handling power faults in a primary electronic device is provided. The method includes setting a power-off duration to an initial value and powering on a hardware interface. In response to detecting a power fault at the hardware interface, the hardware interface is power-cycled by a plurality of power cycles having progressively increasing power-off durations until a limit is reached. A primary electronic device for carrying out the method is also provided. The primary electronic device includes a controller, a memory, and a hardware interface for coupling the telematics device to a secondary electronic device.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method by a primary electronic device, the method for handling power faults on a secondary electronic device coupled to the primary electronic device via a hardware interface of the primary electronic device, the method comprising: detecting a power fault condition on the hardware interface; power-cycling the hardware interface by a plurality of power cycles having a plurality of progressively increasing power-off durations; after each power cycle of the plurality of power cycles, checking the power fault condition; and permanently powering off the hardware interface when the power fault condition is detected and a current power-off duration of the plurality of progressively increasing power-off durations has reached a power-off duration limit. 2. The method of claim 1 , wherein powering off the hardware interface comprises setting, in a persistent storage of the primary electronic device, an indication that the hardware interface has been powered off due to a power fault. 3. The method of claim 2 , further comprising clearing the indication that the hardware interface has been powered off due to the power fault condition in response to detecting that the secondary electronic device has been unplugged from the hardware interface. 4. The method of claim 2 , further comprising checking the indication in the persistent storage upon powering up of the primary electronic device and refraining from powering up the hardware interface in response to determining that the hardware interface has been powered off due to the power fault condition. 5. The method of claim 1 , wherein detecting the power fault condition comprises detecting by a power protection module of the hardware interface one of: an overcurrent condition, an overvoltage condition, and a reverse current condition. 6. The method of claim 1 , wherein detecting the power fault condition on the hardware interface comprises receiving an indication from a power protection module of the power fault condition. 7. The method of claim 6 , wherein receiving the indication from the power protection module comprises receiving a signal change on a pin or receiving an interrupt signal. 8. A primary electronic device, comprising: a controller; a hardware interface coupled to the controller, the hardware interface for coupling the primary electronic device to a secondary electronic device; a memory, coupled to the controller, the memory for storing machine-executable programming instructions which, when executed by the controller, configure the primary electronic device to: in response to detecting a power fault condition on the hardware interface: power-cycle the hardware interface by a plurality of power cycles having progressively increasing power-off durations; after each power cycle of the plurality of power cycles, check the power fault condition; and permanently power off the hardware interface when the power fault condition is detected and a current power-off duration of the progressively increasing power-off durations has reached a power-off duration limit. 9. The primary electronic device of claim 8 , wherein the machine-executable programming instructions which configure the primary electronic device to power off the hardware interface comprise machine-executable programming instructions which configure the primary electronic device to set an indication in a persistent storage thereof that the hardware interface has been powered off due to a power fault. 10. The primary electronic device of claim 9 , wherein the machine-executable programming instructions further comprise machine-executable programming instructions which configure the primary electronic device to clear the indication that the hardware interface has been powered off due to the power fault condition in response to detecting that the secondary electronic device has been unplugged from the hardware interface. 11. The primary electronic device of claim 9 , wherein the machine-executable programming instructions further comprise machine-executable programming instructions which configure the primary electronic device to check the indication in the persistent storage upon powering up of the primary electronic device and refrain from powering up the hardware interface in response to determining that the hardware interface has been powered off due to the power fault condition. 12. The primary electronic device of claim 8 , wherein the machine-executable programming instructions which configure the primary electronic device to detect the power fault condition comprise machine-executable programming instructions which configure the primary electronic device to detect one of: an overcurrent condition, an overvoltage condition, and a reverse current condition. 13. The primary electronic device of claim 8 , wherein the machine-executable programming instructions which configure the primary electronic device to progressively increase the progressively increasing power-off durations comprise machine-executable programming instructions which configure the primary electronic device to increase the current power-off duration between two successive power cycles. 14. The primary electronic device of claim 8 , wherein the machine-executable programming instructions which configure the primary electronic device to detect the power fault condition on the hardware interface comprise machine-executable programming instructions which configure the primary electronic device to receive an indication, from a power protection module of the hardware interface, of the power fault condition. 15. The primary electronic device of claim 14 , wherein the machine-executable programming instructions which configure the primary electronic device to receive the indication from the power protection module comprise machine-executable programming instructions which configure the primary electronic device to receive one of: a signal change on a pin or an interrupt signal. 16. A non-transitory computer-readable medium, storing machine-executable programming instructions which, when executed by a controller, configure a primary electronic device to: in response to detecting a power fault condition on a hardware interface: power-cycle the hardware interface by a plurality of power cycles having progressively increasing power-off durations; after each power cycle of the plurality of power cycles, check the power fault condition; and permanently power off the hardware interface when the power fault condition is detected and a current power-off duration of the progressively increasing power-off durations has reached a power-off duration limit. 17. The non-transitory computer-readable medium of claim 16 , wherein the machine-executable programming instructions which configure the primary electronic device to power off the hardware interface comprise machine-executable programming instructions which configure the primary electronic device to set an indication in a persistent storage thereof that the hardware interface has been powered off due to a power fault. 18. The non-transitory computer-readable medium of claim 17 , wherein the machine-executable programming instructions further comprise machine-executable programming instructions which configure the primary electronic device to clear the indication that the hardware interface has been powered off due to the power fault condition in response to detecting that a secondary electronic device has been unplugged from the hardware interface. 19. The non-transitory computer-readable medium o

Assignees

Inventors

Classifications

  • G06F1/30Primary

    Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24) · CPC title

  • G06F1/266Primary

    Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips · CPC title

  • Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

  • where the computing system component is an input/output interface (interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units G06F13/00) · CPC title

  • where the monitored property is the power consumption (power management in a computing system G06F1/3203) · CPC title

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What does patent US11977427B2 cover?
A method for handling power faults in a primary electronic device is provided. The method includes setting a power-off duration to an initial value and powering on a hardware interface. In response to detecting a power fault at the hardware interface, the hardware interface is power-cycled by a plurality of power cycles having progressively increasing power-off durations until a limit is reache…
Who is the assignee on this patent?
Geotab Inc
What technology area does this patent fall under?
Primary CPC classification G06F1/30. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 07 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).